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WM8944BECS/R 数据表(PDF) 94 Page - Cirrus Logic

部件名 WM8944BECS/R
功能描述  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8944BECS/R 数据表(HTML) 94 Page - Cirrus Logic

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WM8944B
94
Rev 4.3
Device ID
S
A
MSByte Address
(0)
A
MSByte Data 0
A
LSByte Data 0
A
Written to 'Register Address'
A
MSByte Data N
A
LSByte Data N
A
P
Written to 'Register Address+N'
MSByte Data 1
MSByte Data N-2
A
MSByte Data N-1
A
LSByte Data N-1
Written to 'Register Address+N-1'
LSByte Address
A
RW
Figure 38 Multiple Register Write to Specified Address using Auto-increment
Sr
Device ID
S
A
MSByte Address
(0)
A
Device ID
A
(1)
Read from 'Register Address'
MSByte Data 0
LSByte Data 0
A
A
P
MSByte Data N
LSByte Data N
A
A
A
MSByte Data N-1
LSByte Data N-1
A
A
Read from 'Last Register Address+N'
Read from 'Last Register Address+N-1'
LSByte Address
A
RW
RW
Figure 39 Multiple Register Read from Specified Address using Auto-increment
Device ID
A
P
MSByte Data N
(1)
LSByte Data N
A
S
A
A
MSByte Data 0
LSByte Data 0
A
A
MSByte Data N-1
LSByte Data N-1
A
A
Read from 'Last Register Address'
Read from 'Last Register Address+N'
Read from 'Last Register Address+N-1'
MSByte Data 1
LSByte Data 1
A
A
Read from 'Last Register Address+1'
RW
Figure 40 Multiple Register Read from Last Address using Auto-increment
Multiple Write and Multiple Read operations enable the host processor to access sequential blocks of
the data in the WM8944B register map faster than is possible with single register operations. The
auto-increment option is enabled when the AUTO_INC register bit is set. This bit is defined in Table
65. Auto-increment is disabled by default.
3-WIRE (SPI) CONTROL MODE
The 3-wire control interface uses the CS
¯¯ , SCLK and SDA pins.
In 3-wire control mode, a control word consists of 32 bits. The first bit is the read/write bit (R/W), which
is followed by 15 address bits (A14 to A0) that determine which control register is accessed. The
remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register.
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDA pin. The data is
latched on the 32nd falling edge of SCLK after 32 bits of data have been clocked into the device.
In Write operations (R/W=0), all SDA bits are driven by the controlling device.
In Read operations (R/W=1), the SDA pin is driven by the controlling device to clock in the register
address, after which the WM8944B drives the SDA pin to output the applicable data bits.
When the SPI_OD register bit is set, the WM8944B transmits logic 1 by tri-stating the SDA pin, rather
than pulling it high. An external pull-up resistor is required to pull the SDA line high so that the logic 1
can be recognised by the master.
The 3-wire control mode timing is illustrated in Figure 41.



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