LTC6953 datasheet(32/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Figure 22. Block Diagram for JESD204B EZSync Standalone Design Example

EZS_SRQ±

SYNC AND

SYSREF CTRL

M10

SSRQ BIT

ADC0

SYSREF

CLK

ADC1

SYSREF

CLK

DEV CLK

SYSREF

MGMT CLK

FPGA

SYSREF

CLK

DAC1

DAC0

LTC6953

IN±

INPUT/OUTPUT TERMINATIONS AND

AC-COUPLING CAPS NOT SHOWN.

6953 F22

CLOCK

GENERATOR

JESD204B DESIGN EXAMPLE USING EZSync

STANDALONE

This design example consists of a system of two JESD204B

analog-to-digital converters (ADCs), two JESD204B digi-

tal-to-analog converters (DACs) and a JESD204B compat-

ible FPGA. All of the data converters (ADCs and DACs) and

the FPGA require JESD204B subclass 1 device clocks and

SYSREFs, and the FPGA requires an extra management

clock. Additionally, the ADCs require a low noise clock

of less than 100fs total RMS jitter. This leads to a total

of 11 separate signals to generate, with frequencies listed

below. For this example, the SYSREF frequencies for all

devices are the same and should output four pulses upon

a SYSREF request rising edge:

fADC-CLK = 500MHz

fDAC-CLK = 4000MHz

fFPGA-CLK = 125MHz

fFPGA-MGMT = 100MHz

fSYSREF = 12.5MHz

Since the total number of outputs is 11, a single LTC6953

can be used to generate all of the outputs needed as

shown in Figure 22. Note that termination resistors and

AC-coupling caps are not shown for clarity.

Input Assumptions

For this example, assume the input is driven by an exter-

nal clock generator with a frequency of 4000MHz.

fIN = 4000MHz

Design Procedure

Designing and enabling this clock distribution solution

consists of the following steps:

1. Determine all output modes.

2. Determine all M divider values.

3. Determine all digital delay values.

4. Program the IC with the correct divider values, output

delays, and other settings.

5. Synchronize the outputs.

6. Place the SYSREF outputs in a lower power mode until

the next SYSREF request (optional, see Operations

section).

7. Place IC into SYSREF request mode and send a

SYSREF request when needed.

8. Return the IC into SYNC mode (SRQMD = 0) and

place the SYSREF outputs into a lower power mode

for power savings (optional).

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LTC6953 数据表(PDF) 32 Page - Analog Devices

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