LTC6953 datasheet(7/56 Pages) AD

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LTC6953

Rev 0

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Current Deltas from Total Chip

Current

PDx[1:0] = 2 (x = 0 to 10) per Output

–34

PDx[1:0] = 3 (x = 0 to 10) per Output

–68

EZS_SRQ ± State = 1, SSRQ = 1 or SRQMD = 1

+175

Mx = Odd (Not Mx = 1) per Output

+8.6

ADELx = 1 to 31 per Output

+3.0

ADELx = 32 to 63 per Output

+4.7

Additive Phase Noise, Jitter and Spurious (Note 7)

Additive Phase Noise and RMS Jitter

(fIN = 4.5GHz, fOUTx = 4.5GHz, Mx = 1)

Phase Noise Floor

–154.3

dBc/Hz

RMS Jitter, 12kHz to 20MHz Integration BW

fsRMS

RMS Jitter, ADC SNR Method (Note 9)

fsRMS

Additive Phase Noise and RMS Jitter

(fIN = 4.5GHz, fOUTx = 2.25GHz, Mx = 2)

Phase Noise Floor

–157.1

dBc/Hz

RMS Jitter, 12kHz to 20MHz Integration BW

fsRMS

RMS Jitter, ADC SNR Method (Note 9)

fsRMS

Additive Phase Noise and RMS Jitter

(fIN = 4.5GHz, fOUTx = 1.125GHz, Mx = 4)

Phase Noise Floor

–160.2

dBc/Hz

RMS Jitter, 12kHz to 20MHz Integration BW

fsRMS

RMS Jitter, ADC SNR Method (Note 9)

fsRMS

Additive Phase Noise and RMS Jitter

(fIN = 3.2GHz, fOUTx = 200MHz, Mx = 16)

Phase Noise Floor

–167.8

dBc/Hz

RMS Jitter, 12kHz to 20MHz Integration BW

fsRMS

RMS Jitter, ADC SNR Method (Note 9)

fsRMS

Additive Phase Noise and RMS Jitter

(fIN = 3.2GHz, fOUTx = 50MHz, Mx = 64)

Phase Noise Floor

–173.8

dBc/Hz

RMS Jitter, 12kHz to 20MHz Integration BW

fsRMS

RMS Jitter, ADC SNR Method (Note 9)

fsRMS

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VIN+ = VOUT+ = 3.3V unless otherwise specified

(Note 2). All voltages are with respect to GND.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC6953 is guaranteed to meet specified performance

limits over the full operating junction temperature range of –40°C to

125°C. Under maximum operation conditions, airflow or heat sinking

may be required to maintain a junction temperature of 125°C or lower.

It is required that the Exposed Pad (Pin 53) be soldered directly to the

ground plane with an array of thermal vias as described in the Applications

Information section.

Note 3: Absolute maximum time of digital delay is limited to 100µs.

Note 4: For fOUT ≥ 300MHz, analog delay time vs ADELx varies. See

Typical Performance Characteristics plot and the Operation section

Note 5: All outputs configured as enabled clocks: all PDx[1:0] = 0, EZS_

SRQ± pin state = 0, SSRQ = 0, SRQMD = 0, PDALL = 0, PDVCOPK = 0.

Note 6: Configured with six enabled clock outputs and five SYSREF

outputs with output drivers disabled: PD0, PD2, PD4, PD6, PD8, and

PD10 = 0; PD1, PD3, PD5, PD7, and PD9 = 2; EZS_SRQ± pin state = 0;

SSRQ = 0; SRQMD = 0; PDALL = 0; PDVCOPK = 0.

Note 7: Additive phase noise and jitter from LTC6953 only. Incoming

clock phase noise is not included.

Note 8: Measured using DC2610.

Note 9: Additive RMS jitter (ADC SNR method) is calculated by integrating

the distribution section’s measured phase noise floor out to fCLK. Actual

ADC SNR measurements show good agreement with this method.

Note 10: Measured with 36" cables from output of DC2610 to

measurement instrument. Cable loss is NOT accounted for in this plot.

Note 11: Statistics calculated from 1200 total measured parts from two

process lots.

Note 12: Skew is defined as the difference between the zero-crossing time

of a given output and the average zero-crossing time of all outputs.

Note 13: Measured input power is de-embedded to the IN± pins of the

LTC6953.

Note 14: The LTC6953 is driven from a VCO (CVCO55CC-4000-4000)

through a splitter. The other side of the splitter drives the input of a

LTC6952 to lock the VCO in a PLL. The reference for the LTC6952 PLL is

a Pascal OCXO-E, fREF = 100MHz, PREF = 6dBm.

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