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LTC6953 数据表(PDF) 18 Page - Analog Devices |
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LTC6953 数据表(HTML) 18 Page - Analog Devices |
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18 / 56 page ![]() LTC6953 18 Rev 0 For more information www.analog.com Preliminary Technical Data Advance Product Information Subject to Change Rev PrA OPERATION Table 8. Parameters and Limitations of EZSync and ParallelSync (Two Stages Only) EZSync STANDALONE (SEE FIGURE 5) EZSync MULTICHIP ParallelSync MULTICHIP PIN CONTROLLED REQUESTS (SEE FIGURE 6) REQUEST PASS-THROUGH (SEE FIGURE 7) GENERAL REFERENCE DISTRIBUTION (SEE FIGURE 8) LTC6953 REFERENCE DISTRIBUTION SEE FIGURE 9) CONTROLLER FOLLOWER CONTROLLER FOLLOWER RMS Jittera ~75fs ~75fs ~105fs ~75fs ~105fs ~75fs ~75fs Possible Number of Followers (Nfol) – 1 to 11 1 to 5 – – Possible Number of Parallel Parts (Npar) – – – Unlimitedb 1 to 5 Total Number of Outputs 11 11 Nfol 11 Nfol 11 – 2 Nfol 11 Nfol 11 Npar 11 Npar Maximum Number of Outputs 11 121 56 Unlimitedb 55 Maximum Skew tSKEW ~ tSKEW + tPDc ~ tSKEW + tPDc ~tSKEWd ~tSKEWd SYNC Timing Easy Easy Easy Moderate Easy SYSREF Request Timing Easy Moderate Easy Moderate Easy Number of External VCOs 1 1 1 Npar Npar Software SYNC/SYSREF Request? Yes No Yes No Yes a Assumes ADC SNR equivalent integrated PLL/VCO RMS jitter contribution of 27fs and additive jitter for distribution-only parts of 70fs. b The only limitation is the ability to distribute the reference accurately. c Assumes worst-case skew between CONTROLLER and FOLLOWER outputs. Dependent on propagation delay of FOLLOWER and skew of controller-to- follower routing. d Dependent on skew of reference distribution parts, reference routing and individual part-to-part skew. Table 7. Settings of EZMD and PARSYNC for Different Synchronization Topologies CONTROL BIT EZSync STANDALONE (SEE FIGURE 5) EZSync MULTICHIP (SEE FIGURES 6 AND 7) ParallelSync MULTICHIP (SEE FIGURES 8 AND 9) CONTROLLER FOLLOWER PARSYNC (LTC6952 Only) 0 0 0 1 EZMD 0 0 1 0 |
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