LTC6953 datasheet(20/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

FOLLOWER before the FOLLOWER outputs or any fol-

lower-synchronous CONTROLLER outputs start clocking.

Additionally, a CONTROLLER must have bit EZMD set to

“0” and a FOLLOWER must have both EZMD and PDPLL

set to “1”. See the Applications Information section for a

programming example. Additionally, the LTC6952Wizard

provides programming guidance.

ParallelSync

In a ParallelSync application, multiple ParallelSync com-

patible devices are connected in parallel with a shared dis-

tributed REF signal as shown in Figure 8. The advantage of

parallel connection is improved jitter performance, as the

clock signals do not propagate through two or more cas-

caded devices. However, synchronization requires tighter

control of the SYNC and SYSREF request (SRQ) signals’

timing because of the need to have the SYNC/SRQ edges

fall within the same REF cycle for all connected devices.

The LTC6953 is not compatible as a ParallelSync device

except as part of the reference and EZS_SRQ distribution

OPERATION

160Ω

100Ω

160Ω

100Ω

160Ω

100Ω

160Ω

100Ω

160Ω

100Ω

OUTx ±

EZS_SRQ+

OUT0+

OUT1+

EZS_SRQ+

EZS_SRQ–

OUT10+

OUT2+

OUT3+

OUT4+

OUT5+

OUT6+

OUT7+

OUT8+

OUT9+

11 OUTPUTS

LTC6953

EZSync

CONTROLLER

SYNC OR SYSREF

REQUEST: TOGGLE PIN

OR WRITE SSRQ BIT

OUT0–

OUT1–

OUTx ±

11 OUTPUTS

OUT2–

OUT3–

OUTx ±

11 OUTPUTS

OUTX±

11 OUTPUTS

OUT4–

OUT5–

OUT6–

OUT7–

OUTx ±

11 OUTPUTS

OUT10–

OUT8–

OUT9–

EZS_SRQ–

FOLLOWER-SYNCHRONOUS OUTPUT

ALL CONTROLLER TO FOLLOWER

CONNECTIONS MUST BE DC-COUPLED

CONTROLLER

FOLLOWERS

6953 F07

IN+

LTC6953

IN–

IN+

IN–

IN+

IN–

IN+

IN–

IN+

IN–

LTC6953

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

IN±

CLOCK

GENERATOR

Figure 7. EZSync Multichip Synchronization with

Request Pass-Through

or LTC6952 FOLLOWERS). This request pass-through

configuration reduces the system complexity at the cost

of fewer possible FOLLOWERS (a maximum of 5). Note

that MPx for the CONTROLLER’s pass-through output

must be set greater than 0.

For all cases of EZSync synchronization, the CONTROLLER

must be programmed to output seven pre-pulses to each

REF±

OUTx ±

EZS_SRQ±

LF(S)

VCO±

LTC6952 #1

REF±

OUTx ±

EZS_SRQ±

LF(S)

VCO±

LTC6952 #2

REF±

OUTx ±

EZS_SRQ±

VCO±

LTC6952 #3

REF±

OUTx ±

EZS_SRQ±

VCO±

LTC6952 #N

LF(S)

11 OUTPUTS

VCO

REFERENCE

DISTRIBUTION

EZS_SRQ

DISTRIBUTION

REFERENCE MAY BE SINGLE-

ENDED OR DIFFERENTIAL

EZS_SRQ MAY BE SINGLE-

ENDED OR DIFFERENTIAL

6953 F08

Figure 8. ParallelSync Multichip Synchronization

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