LTC6953 datasheet(40/56 Pages) AD

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LTC6953

Rev 0

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

2. For each device clock/SYSREF pair, subtract half a

device clock period from DDELSYSvalid to find the

SYSREF delay. This is equivalent to subtracting the

corresponding divide value of the device clock:

DDELADC–SYS´ = DDELSYSvalid – MADC–CLK

DDELADC–SYS´ = 32 – 8 = 24

DDELDAC–SYS´ = DDELSYSvalid – MDAC–CLK

DDELDAC–SYS´ = 32 – 1 = 31

DDELFPGA–SYS´ = DDELSYSvalid – MFPGA–CLK

DDELFPGA–SYS´ = 32 – 32 = 0

3. Adjust for CONTROLLER vs FOLLOWER outputs.

Any CONTROLLER output that is synchronous with

the FOLLOWER must have the delay offset from

Equation 8 added to its DDEL value. FOLLOWER out-

puts need no adjustment. For this example, the ADC

CLKs and SYSREFs come from the CONTROLLER:

DDELADC–CLK = DDELADC–CLK´ + DDELFS–OS

DDELADC–CLK = 32 + 14 = 46

DDELADC–SYS = DDELADC–SYS´ + DDELFS–OS

DDELADC–SYS = 24 + 14 = 38

DDELDAC–CLK = DDELDAC–CLK´ + 0 = 32

DDELDAC–SYS = DDELDAC–SYS´ + 0 = 31

DDELFPGA–CLK = DDELFPGA–CLK´ + 0 = 32

DDELFPGA–SYS = DDELFPGA–SYS´ + 0 = 0

Even though CONTROLLER OUT9 is only passing

through the SYNC/SRQ pulse, its digital delay should

be set so that its edges occur at the same time as

the latest occurring SYSREF in the overall system.

This is to ensure that future SYSREF requests are

aligned properly. Note that the delay offset from 8

will need to be added as well since it is located on

the CONTROLLER part. The latest occurring SYSREF

is the DAC SYSREF, therefore:

DDELOUT9 = DDELDAC–SYS + DDELFS–OS

DDELOUT9 = 31 + 14 = 45

The follower-driver digital delay is set to 0 in this

example:

DDELFD = DDELOUT8 = 0

Table 18 summarizes the DDEL settings for all outputs.

Table 18. O]utput DDELx Settings for EZSync Multichip Design

Example

OUTPUT

PURPOSE

DDELx

OUT0

ADC0 SYSREF

OUT1

ADC0 CLK

OUT2

ADC1 SYSREF

OUT3

ADC1 CLK

OUT4

ADC2 SYSREF

OUT5

ADC2 CLK

OUT6

ADC3 SYSREF

OUT7

ADC3 CLK

OUT8

FOLLOWER Input

OUT9

FOLLOWER EZS_SRQ

OUT10

FPGA MGMT CLK

OUT0

Unused

N/A

OUT1

FPGA SYSREF

OUT2

FPGA DEV CLK

OUT3

DAC0 SYSREF

OUT4

DAC0 CLK

OUT5

DAC1 SYSREF

OUT6

DAC1 CLK

OUT7

DAC2 SYSREF

OUT8

DAC2 CLK

OUT9

DAC3 SYSREF

OUT10

DAC3 CLK

Now that the output divider and delays have been deter-

mined, the ICs can be programmed.

Status Register Programming

This example will use the STAT pin to alert the system

whenever the LTC6953 generates a fault condition. For

the CONTROLLER and FOLLOWER, program x[3] = 1 to

force the STAT pin high whenever the VCOOK flag asserts:

CONTROLLER Reg01 = h08

FOLLOWER Reg01 = h08

Power and FILT Register Programming

For correct operation on both CONTROLLER and

FOLLOWER, all internal blocks should be enabled.

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