LTC6953 datasheet(43/56 Pages) AD

43 / 56 page

LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Figure 27. Outputs After Synchronization for the EZSync Multichip Design Example (SRQMD = 0)

Figure 28. Outputs After SYSREF Request for the EZSync Multichip Design Example (SRQMD = 1)

ADC DEVICE CLOCKS

(OUT1, 3, 5 AND 7)

FOLLOWER DRIVER

(OUT8)

SYNC PASS-THROUGH

(OUT9)

tPD

ADC SYSREFs

(MUTED OUT0, 2, 4 AND 6)

DAC DEVICE CLOCKS

(OUT4, 6, 8 AND 10)

FOLLOWER OUTPUTS

CONTROLLER OUTPUTS

DAC SYSREFs

(MUTED OUT3, 5, 7 AND 9)

FPGA SYSREF

(MUTED OUT1)

FPGA MANAGEMENT CLOCK

(OUT 2)

SYSREF VALID CLOCK EDGE

NOT SYNCHRONIZED, PHASE UNDETERMINED

6953 F27

FPGA DEVICE CLOCK

(OUT2)

INTERNAL ADC SYSREF DIVIDERS

(MUTED OUT0, 2, 4 AND 6)

INTERNAL DAC SYSREF DIVIDERS

(MUTED OUT3, 5, 7 AND 9)

INTERNAL FPGA SYSREF DIVIDER

(MUTED OUT1)

EZS_SRQ or SSRQ BIT

EZS_SRQ OR SSRQ BIT

CONTROLLER OUTPUTS

FOLLOWER OUTPUTS

6953 F28

FOLLOWER DRIVER

(OUT8)

SYSREQ PASS-THROUGH

(OUT9)

ADC DEVICE CLOCKS

(OUT1, 3, 5 AND 7)

ADC SYSREFs

(OUT0, 2, 4 AND 6)

DAC DEVICE CLOCKS

(OUT4, 6, 8 AND 10)

DAC SYSREFs

(OUT3, 5, 7 AND 9)

FPGA SYSREF

(OUT1)

FPGA DEVICE CLOCK

(OUT2)

4000MHz

FPGA MANAGEMENT CLOCK

(OUT10)

100MHz

4000MHz

125MHz

500MHz

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