LTC6953 datasheet(17/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

When the EZS_SRQ input is driven back low or “0” is writ-

ten to the SSRQ bit, the synchronized internal dividers will

start after an initial latency. Outputs with DDELx ≠ 0 will

be delayed by an extra DDELx/2 input cycles. The behavior

of each output will be defined individually by the output’s

corresponding SRQENx and MODEx bits as shown in

Table 5. All dividers with the same DDELx delay setting

will have their output rising edge occur within the skew

times as defined in the Electrical Characteristics table. The

range of each delay is 0 to 4095 input half cycles and is

independent of the divide ratio setting of each divider. See

the Applications Information section for synchronization

programming examples. Additionally, the LTC6952Wizard

may be used to visualize these timing relationships.

Table 5. Synchronization (SRQMD = 0) Output Behavior vs

Device Settings

SRQENx

MODEx

INTERNAL

DIVIDER

SYNC TO

OTHER

DIVIDERS

INTERNAL

DIVIDER

START

LATENCY

FROM SYNC

SIGNAL

FALLING EDGE

(DDELx = 0)

OUTPUT

BEHAVIOR

N/A

Free Running

1, 2 or 3

Muted

Yes

~45µs + 7/ fIN

Mute on SYNC

High, Run on

Sync Low

1 or 3

Muted

Sync Signal

Pass-Through

SYSREF Generation Overview

The JESD204B subclass 1 specification describes a

method to align multiple data converter devices (ADCs or

DACs) in time and provide repeatable and programmable

latency across the serial link with a logic device (FPGA).

The Local Multi-Frame Clocks (LMFC) and internal clock

dividers on all devices in the system are synchronized by a

pulse (or pulse train) named SYSREF. Care must be taken

to make sure the SYSREF signal remains synchronized to

the ADC, DAC, and FPGA clocks and meets setup and hold

timing as specified by the devices.

The LTC6953 supports three different methods of SYSREF

generation as described in the JESD204B specification:

•

Free running

•

Gated on/off by a SYSREF request signal

•

One, two, four or eight SYSREF pulses after the rising

edge of a SYSREF request signal

These modes are defined by each output’s individually

programmable MODEx bits. In order to generate SYSREF

pulses, bit SRQMD must be set to “1” and MPx must be

greater than 0. SYSREF requests (SYSREQ) are applied

on the EZS_SRQ± pins or by setting the SSRQ bit to “1”.

Table 6 describes the output behavior in SYSREF genera-

tion mode. Bits SYSCT[1:0] can be found in register h0B.

Note that synchronization MUST be completed prior to

SYSREF generation as described in the Synchronization

Overview.

Table 6. Output Behavior in SYSREF Generation Mode

(SRQMD = 1)

SRQENx MODEx

OUTPUT BEHAVIOR

Free Run, Ignore SYSREQ

1, 2

or 3

Muted,Ignore SYSREQ

Free Run, Ignore SYSREQ

Gated Pulses: Run on SYSREQ High, Mute on Low

SYSREQ Pass-Through

Output 2SYSCT Pulses After SYSREQ Goes High

Multichip Synchronization and SYSREF Generation

Using one LTC6953 in EZSync Standalone configuration

(Figure 5), up to eleven clock signals or SYSREFs can

be generated and synchronized. For applications requir-

ing more than eleven clock outputs, the LTC6953 and

its companion chip, the LTC6952, support two methods

of multichip synchronization and SYSREF generation:

EZSync Multichip and ParallelSync. The synchronization

configuration is determined by bits EZMD and PARSYNC

(on the LTC6952 only), and their required settings are

shown in Table 7. Table 8 introduces the important attri-

butes of these methods and their variants, with further

details provided in the following paragraphs. Note that

this table only refers to two-stage applications. Many

more outputs are possible by using more stages.

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