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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

INTRODUCTION

The purpose of a clock distributor is to take an incom-

ing clock signal of frequency fIN and produce multiple

new clock signals at the same frequency or some other

frequency value divided down from the input frequency.

Each output clock can have its phase individually adjusted

relative to the other clocks through the synchronization

process. Figure 19 shows a typical application of the

LTC6953.

APPLICATIONS INFORMATION

Figure 19. LTC6953 Typical Application

75Ω

30Ω

10nF

IN+

IN–

M0 DIV, DDEL,

AND ADEL

OUT0

OUT10

M10 DIV, DDEL,

AND ADEL

M1 DIV, DDEL,

AND ADEL

OUT1

LTC6953

(fOUT0)

(fOUT1)

(fOUT10)

(fIN)

÷M0

÷M1

÷M10

6953 F19

CLOCK

GENERATOR

OUTPUT FREQUENCY

For a given input frequency fIN, the output frequency fOUTx

produced at the output of the Mx dividers is given by

Equation 4:

fOUTx =

fIN

(4)

DIGITAL AND ANALOG OUTPUT DELAYS

Synchronization allows the start times of each output

divider to be delayed by the value programmed into the

digital delay bits (DDELx), expressed in ½ input cycles.

Applications needing to calculate the delay in terms of time

can use Equation 5 where DDELx is DDEL0 to DDEL10:

tDDELx =

DDELx

2 • fIN

(

)

(5)

The analog delay blocks (ADELx) are useful in trimming

signal timing differences caused by non-ideal PCB rout-

ing. This is effective for optimizing setup and hold times

for SYSREFs versus device clocks in JESD204B appli-

cations. Unlike digital delay, adding analog delay will

adversely affect the jitter performance. Add analog delay

to the SYSREF path whenever possible to minimize the

impact on the device clocks. For example, if the SYSREF

signal in a SYSREF/Clock pair is arriving at the destination

device too late, it is better to add one digital delay code to

the device clock and then add analog delay to the SYSREF,

if necessary, to bring it closer to the device clock.

The approximated analog delay time can be calculated in

picoseconds (ps) by Equations 6 (for ADELx < 32) and

Equation 7 (for ADELx ≥ 32) while adhering to the fre-

quency limitations described in Table 4.

ADELx = 1 to 31:

t ADEL = [ 11.25 • ADELx + 93.8

(

)

–2.5

0.00285 • fOUT

(

)

2.5

] –0.4

(6)

ADELx = 32 to 63:

t ADEL = [ 26 • ADELx – 517

(

)

–2.5

0.00125 • fOUT

(

)

2.5

] –0.4

(7)

where fOUT is the output frequency in GHz. The

LTC6952Wizard may be used for analog delay calcula-

tion and visualization.

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