LTC6953 datasheet(21/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

as described below. See the LTC6952 data sheet for more

information on ParallelSync.

The SYNC/SRQ timing for ParallelSync can be simpli-

fied to a single software bit write by using an LTC6953

(or LTC6952 with its PLL disabled) as the reference and

EZS_SRQ distribution block, as shown in Figure 9. In this

application, the EZS_SRQ outputs of the reference distri-

bution part should be set to transition on the falling edge

of its corresponding reference clock output. To achieve

this, first synchronize the reference distribution part using

100Ω

OUTx ±

EZS_SRQ+

REF+

OUT0+

OUT1+

EZS_SRQ+

EZS_SRQ–

OUT10+

OUT2+

OUT3+

OUT4+

OUT5+

OUT6+

OUT7+

OUT8+

OUT9+

LTC6952 #1

11 OUTPUTS

IN±

REF IN

LTC6953

REFERENCE

DISTRIBUTION

SYNC OR SYSREF

REQUEST: TOGGLE PIN

OR WRITE SSRQ BIT

OUT0–

REF –

LTC6952 #2

OUT1–

OUTx ±

LTC6952 #3

11 OUTPUTS

LTC6952 #4

OUT2–

OUT3–

OUTx ±

11 OUTPUTS

OUTx ±

11 OUTPUTS

OUT4–

OUT5–

OUT6–

OUT7–

OUTx ±

11 OUTPUTS

LTC6952 #5

OUT10–

OUT8–

OUT9–

EZS_SRQ–

1 OUTPUT

EZS-SRQ CONNECTIONS

MUST BE DC-COUPLED

LF(S)

VCO±

VCO

LF(S)

VCO±

VCO

LF(S)

VCO±

VCO

LF(S)

VCO±

VCO

LF(S)

VCO±

VCO

REF+

REF –

REF+

REF –

REF+

REF –

REF+

REF –

6953 F09

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

Figure 9. ParallelSync Multichip Synchronization with

LTC6953 or LTC6952 Reference Distribution

the settings given in Table 9, where DDELREF can be any

valid DDEL value.

Table 9. Reference Distribution Divider and DDEL Settings

for ParallelSync

REF CLK

DIVIDE

REF CLK DDEL

EZS_SRQ

DIVIDE

EZS_SRQ DDEL

DDELREF

DDELREF + 1

DDELREF

DDELREF + 2

DDELREF

DDELREF + 3

DDELREF

DDELREF + 4

REF Divide > 4

DDELREF

= REF Divide

DDELREF

Just before sending a SYNC or SYSREF request to the par-

allel parts, set the reference distribution part’s SRQMD bit

to “1”. This will automatically retime the passed-through

requests to the reference clocks. After the request is done,

set the SRQMD bit back to “0” to save supply current

from the reference distribution part. See the Applications

Information section for a programming example.

To determine the best configuration for a given applica-

tion, the flowchart in Figure 10 can be used. This flowchart

uses the parameters from Table 8 to guide the user to the

most suitable configuration.

Depending on the user’s system requirements, many sim-

plifications or additions can be made for multiple chip

synchronization. For example, the above applications only

assume a maximum of two stages, even though more

stages can be added to increase the number of outputs.

However, these applications are beyond the scope of this

data sheet. Please contact the factory.

Power Savings in SYSREF Generation Mode

In most applications, SYSREF requests are a rare occur-

rence. The LTC6953 provides modes to shut down as

much circuitry as possible while still maintaining the

correct timing relationship between SYSREF outputs and

clock outputs. Individual outputs may be put into a low

power mode while leaving the internal dividers running

by writing a “2” to the PDx bits, where x is the output of

interest. Additionally, putting the LTC6953 into SYSREF

generation mode (SRQMD = 1) causes the part to draw a

significantly higher current than SRQMD = 0. Therefore,

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