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LTC6953

Rev 0

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

Any divider can be muted or powered down to save cur-

rent by adjusting its corresponding PDx[1:0] bits. The

description of the PDx[1:0] bits is shown in Table 3.

Table 3. PDx[1:0] Programming

PDx[1:0]

DESCRIPTION

Normal Operation

Mute Output (OUTx = 0 If OINVx = 0, OUTx = 1 If OINVx = 1),

Internal Divider Remains Running and Synchronized

Power-Down Output (Both + and – Outputs Go to VOUT+),

Internal Divider Remains Running and Synchronized

Power-Down Divider and Output (Both + and – Outputs

Go to VOUT+), Internal Divider Stops and Must Be

Re-Synchronized Upon Return to Normal Operation

DIGITAL OUTPUT DELAYS (DDEL0 TO DDEL10)

Each output divider can have the start time of the output

delayed by integer multiples of ½ of the input period after

a synchronization event. The digital delay value is pro-

grammed into the DDELx[11:0] bits and can be any value

from 0 to 4095. Digital delays are only enabled when the

synchronization bits SRQENx are set to “1”, and any changes

to the output digital delays will not be reflected until after

synchronization. Digital delay can be used with no degrada-

tion to clock jitter performance. See the Operation section

on Synchronization and the Applications Information sec-

tion for details on the use of the digital delay settings.

ANALOG OUTPUT DELAYS (ADEL0 TO ADEL10)

Each output has a fine analog delay feature to further

adjust its output delay time (tADELX) in small steps con-

trolled by the ADELx[5:0] bits. For output frequencies less

than 300MHz, absolute time delays range from 0 to 1.1ns.

Above 300MHz, the time delay is frequency dependent,

and the valid useful range of ADELx is reduced according

to Table 4.

Table 4. Maximum ADELx vs Output Frequency Range

fOUT RANGE

MAXIMUM ADELx

fOUTx ≤ 750MHz

750MHz < fOUTx ≤ 1GHz

1GHz < fOUTx ≤ 1.5GHz

1.5GHz < fOUTx ≤ 1.75GHz

1.75GHz < fOUTx ≤ 2.25GHz

fOUTx > 2.25GHz

OPERATION

Figure 2 shows the approximate analog delay time

(tADELx) vs ADELx and output frequency. Note that the

y-axis is logarithmic scale, and that analog delay is zero

for ADEL = 0. See the Applications Information section

for a more comprehensive method of calculating expected

analog delay.

Figure 2. Analog Delay Time vs ADEL Code and

Output Frequency

< 300MHz

500MHz

750MHz

1GHz

1.5GHz

1.75GHz

2.25GHz

ADEL CODE

160

320

640

1280

6953 F02

Use caution when using analog delay on device clocks

as this will degrade jitter. Digital delay should be used

whenever possible since it does not impact performance.

The maximum value of analog delay will never need to be

more than half of an input period.

Analog delays are always enabled regardless of the value

of the SRQENx bits, and they take effect immediately

upon a write to the ADELx registers. However, changes

in ADEL can cause the output to glitch temporarily, espe-

cially switching between ADEL = 0 and ADEL ≠ 0. See the

Applications Information section for details on the use of

the analog delay settings. The LTC6952Wizard may be

used for ADEL calculation and visualization.

CML OUTPUT BUFFERS (OUT0 TO OUT10)

All of the outputs are very low noise, low skew 2.5V CML

buffers. Each output can be either AC- or DC-coupled,

and terminated with 100Ω differentially. If a single-ended

output is desired, each side of the CML output can be

individually AC-coupled and terminated with 50Ω. The

OINVx bits can selectively invert the sense of each out-

put to facilitate board routing without having to cross

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