LTC6953 datasheet(38/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

shows a block diagram of the full system. OUT8 of the

CONTROLLER LTC6953 is driving the IN± inputs of the

FOLLOWER LTC6953. This output is referred to as the

“follower-driver” output. OUT9 of the CONTROLLER is

driving the EZS_SRQ± pins of the FOLLOWER, and is

therefore the SYNC/SRQ pass-through output. Also notice

that the CONTROLLER clock outputs are the lowest jitter

clocks, and should therefore be used to drive the ADCs.

Input Assumptions

For this example, assume the input to the CONTROLLER

LTC6953 is driven by an external clock generator with a

frequency of 4000MHz.

fIN = 4000MHz

Design Procedure

Designing and enabling this clock distribution solution

consists of the following steps:

1. Determine all output modes for CONTROLLER and

FOLLOWER.

2. Determine all M divider values.

3. Determine all digital delay values.

4. Program the ICs with the correct divider values, out-

put delays, and other settings.

5. Synchronize the outputs.

6. Place the SYSREF outputs in a lower power mode until

the next SYSREF request (optional, see Operations

section).

7. Place ICs into SYSREF request mode and send a

SYSREF request when needed.

8. Return the IC into SYNC mode (SRQMD = 0) and

place the SYSREF outputs into a lower power mode

for power savings (optional).

Note that synchronization MUST be performed before a

SYSREF request. The synchronization must be repeated

only if the divider setting is changed or if the divider is

powered down.

Determining Output Modes

All outputs can be programmed as clocks (MODEx = 0),

SYSREFs (MODEx = 1 or 3) or SYNC/SRQ pass-through

outputs (MODEx = 2) using each output’s individual

MODEx bits as described in Table 5 and Table 6. Any out-

put can also be programmed to ignore SYNC and SYSREF

requests by setting that output’s corresponding SRQENx

bit to “0”. Noting that this design example calls for pulsed

SYSREFs (MODEx = 3) and that the FPGA management

clock should always be free running (CONTROLLER

SRQEN10 = 0), Table 16 summarizes each output’s

mode settings.

Table 16. Output Mode Settings for EZSync Multichip

Design Example

OUTPUT

PURPOSE

SRQENx

MODEx

PDx

OUT0

ADC0 SYSREF

OUT1

ADC0 CLK

OUT2

ADC1 SYSREF

OUT3

ADC1 CLK

OUT4

ADC2 SYSREF

OUT5

ADC2 CLK

OUT6

ADC3 SYSREF

OUT7

ADC3 CLK

OUT8

To FOLLOWER IN±

OUT9

FOLLOWER

EZS_SRQ

OUT10

FPGA MGMT CLK

OUT0

Unused

OUT1

FPGA SYSREF

OUT2

FPGA DEV CLK

OUT3

DAC0 SYSREF

OUT4

DAC0 CLK

OUT5

DAC1 SYSREF

OUT6

DAC1 CLK

OUT7

DAC2 SYSREF

OUT8

DAC2 CLK

OUT9

DAC3 SYSREF

OUT10

DAC3 CLK

Determining Output Divider Values

Once the desired frequencies of the outputs are deter-

mined, the output divider values can be calculated.

The ADC, DAC and FPGA clock frequencies are already

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