LTC6953 datasheet(44/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

JESD204B DESIGN EXAMPLE USING ParallelSync

This design example consists of a system of eight

JESD204B analog-to-digital converters (ADCs) and a

JESD204B compatible FPGA. All of the ADCs and the

FPGA require JESD204B subclass 1 device clocks and

SYSREFs, and the FPGA requires an extra management

clock. Additionally, the ADCs require low noise clocks of

less than 100fs total RMS jitter. This leads to a total of

19 separate signals to generate, with frequencies listed

below. For this example, the SYSREF frequencies for all

devices are the same and should output four pulses upon

a SYSREF request rising edge:

fADC–CLK = 294.912MHz

fFPGA–CLK = 147.456MHz

fFPGA–MGMT = 98.304MHz

fSYSREF = 9.216MHz

To determine which multichip configuration to use, we uti-

lize the flowchart in Figure 10. This example has nine total

JESD204B device clock/SYSREF pairs, eight of which need

to be less than 100fs total jitter. We also need one additional

non-low noise standalone clock for the FPGA. Therefore:

TP = 9

LNP = 8

TS = 1

LNS = 0

Based on these inputs, Figure 10 suggests using the

ParallelSync multichip protocol with LTC6953 reference

distribution topology shown in Figure 9, using one LTC6953

as the reference distribution chip (REF LTC6953) and two

LTC6952s in parallel to generate the clocks (LTC6952 #1

and LTC6952 #2). Figure 29 shows a block diagram of

the full system. Note that OUT0 of the reference LTC6953

is driving the REF± inputs of LTC6952 #1 and OUT1 is

driving the EZS_SRQ± pins of LTC6952 #1. Likewise,

OUT2 of the reference LTC6953 is driving the REF± inputs

of LTC6952 #2 and OUT3 is driving the EZS_SRQ± pins

of LTC6952 #2. All outputs in this configuration are low

RMS jitter (~75fs ADC SNR Method).

Although the ParallelSync design example has been

shown here for reference, most of the design work for it

involves the LTC6952. Please refer to the LTC6952 data

sheet for detailed instructions on programming the ICs

for this example.

SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES

Care must be taken when creating a PCB layout to mini-

mize power supply decoupling and ground inductances.

All power supply V+ pins should be bypassed directly to

the ground plane using either a 0.01µF or a 0.1µF ceramic

capacitor as called out in the Pin Functions section as

close to the pin as possible. Multiple vias to the ground

plane should be used for all ground connections, includ-

ing to the power supply decoupling capacitors.

The package’s exposed pad is a ground connection, and

must be soldered directly to the PCB land. The PCB land

pattern should have multiple thermal vias to the ground

plane for both low ground inductance and also low ther-

mal resistance (see Figure 30 for an example). An example

of grounding for electrical and thermal performance can

be found on the DC2610 layout.

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