LTC6953 datasheet(11/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

PIN FUNCTIONS

CS (Pin 1): Serial Port Chip Select. This CMOS input initi-

ates a serial port communication burst when driven low,

ending the burst when driven back high. See the Operation

section for more details.

VD+ (Pin 2): 3.15V to 3.45V Positive Supply Pins for

Synchronization/SYSREF Request Functions and Serial

Port. This pin should be bypassed directly to the ground

plane using a 0.01µF ceramic capacitor as close to the

pin as possible.

OUT0+, OUT0– (Pins 34, 33): Output Signals. The output

divider is buffered and presented differentially on these

pins. The outputs have 50Ω (typical) output resistance

per side (100Ω differential). The far end of the trans-

mission line is typically terminated with 100Ω connected

across the outputs. See the Operation and Applications

Information section for more details.

OUT1+, OUT1– (Pins 31, 30): Same as OUT0.

OUT2+, OUT2– (Pins 28, 27): Same as OUT0.

OUT3+, OUT3– (Pins 25, 24): Same as OUT0.

OUT4+, OUT4– (Pins 22, 21): Same as OUT0.

OUT5+, OUT5– (Pins 19, 18): Same as OUT0.

OUT6+, OUT6– (Pins 16, 15): Same as OUT0.

OUT7+, OUT7– (Pins 13, 12): Same as OUT0.

OUT8+, OUT8– (Pins 10, 9): Same as OUT0.

OUT9+, OUT9– (Pins 7, 6): Same as OUT0.

OUT10+, OUT10– (Pins 4, 3): Same as OUT0.

VOUT+ (Pins 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35):

3.15V to 3.45V Positive Supply Pins for Output Dividers.

Each pin should be separately bypassed directly to the

ground plane using a 0.01µF ceramic capacitor as close

to the pin as possible.

NC (Pins 36, 42, 43, 45, 46): Not Connected Internally.

It is recommended that these pins be connected to the

ground pad (pin 53).

IN+, IN– (Pins 37, 38): Input Signals. The differential

signal placed on these pins is buffered with a low noise

amplifier and fed to the internal distribution path. These

self-biased inputs present a differential 250Ω (typical)

resistance to aid impedance matching. They may also be

driven single-ended by using the matching circuit in the

Operation section.

VIN+ (Pins 39): 3.15V to 3.45V Positive Supply Pin for

Input Circuitry. This pin should be bypassed directly to the

ground plane using a 0.01µF ceramic capacitor as close

to the pin as possible.

SD (Pin 40): Chip Shutdown Pin. When tied to GND, this

CMOS input disables all blocks in the chip. This is the

same function as PDALL in the serial interface.

GND (Pin 41): Negative Power Supply (Ground). This pin

should be tied directly to the ground pad (Pin 53).

VREF+ (Pin 44): 3.15V to 3.45V Positive Supply Pin for

EZS_SRQ circuitry. This pin should be bypassed directly

to the ground plane using a 0.1µF ceramic capacitor as

close to the pin as possible.

EZS_SRQ+, EZS_SRQ– (Pins 47, 48): Synchronization

or SYSREF Request Input. Bit SRQMD defines this dif-

ferential or single-ended input as an EZSync request or

SYSREF request. It can operate as a differential input,

or EZS_SRQ– can be tied to GND and EZS_SRQ+ driven

with a single-ended CMOS signal. See the Operation and

Applications Information sections for more details.

STAT (Pin 49): Status Output. This signal is a configurable

logical OR combination of the VCOOK and VCOOK status

bits, programmable via the STATUS register. It can also

be configured to present a diode voltage for temperature

measurement. See the Operation section for more details.

SCLK (Pin 50): Serial Port Clock. This CMOS input clocks

serial port input data on its rising edge. See the Operation

section for more details.

SDO (Pin 51): Serial Port Data Output. This CMOS three-

state output presents data from the serial port during a

read communication burst. Optionally attach a resistor

of > 200kΩ to GND to prevent a floating output. See the

Operation section for more details.

SDI (Pin 52): Serial Port Data Input. The serial port uses

this CMOS input for data. See the Operation section for

more details.

GND (Exposed Pad Pin 53): Negative Power Supply

(Ground). The package exposed pad must be soldered

directly to the PCB land. The PCB land pattern should

have multiple thermal vias to the ground plane for both

low ground inductance and also low thermal resistance.

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