LTC6953 datasheet(48/56 Pages) AD

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LTC6953

Rev 0

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Figure 34. Simplified Sample Clock Input Circuit

TOTAL CLOCK

JITTER (RMS)

10fs

20fs

50fs

100fs

200fs

500fs

1ps

FREQUENCY OF FULL–SCALE INPUT SIGNAL (GHz)

0.01

0.1

104

114

124

6953 F33

Figure 33. SNR vs Input Signal Frequency vs

Sample Clock Jitter

These calculations are also theoretical. They assume a

noiseless ADC with infinite resolution. All realistic ADCs

have both added noise and a resolution limit. The limita-

tions of the ADC must be accounted for to prevent over-

specifying the sampling clock.

Figure 33 plots the previous equations and provides a

simple, quick way to estimate the sampling clock jitter

requirement for a given input signal or the expected SNR

performance for a given sample clock jitter.

the ADC analog input. A non-jitter dominated SNR mea-

surement (SNRbase) is created by applying a very low

amplitude (or low frequency) sinewave to the ADC analog

input. The total clock jitter (tJ(TOTAL)) can be calculated

using Equation 12.

t J(TOTAL) =

10 –

log10 10 –

SNR jitter

–10

– 10 –

SNRbase

⎛

⎝

⎜

⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

2πfIN

(12)

Assuming the inherent aperture jitter of the ADC (tJ(ADC))

is known, the jitter of the clock generator (tJ(CLK)) is

obtained using Equation 9.

ADC SAMPLE CLOCK INPUT DRIVE REQUIREMENTS

Modern high speed, high resolution ADCs are incredibly

sensitive components able to match or exceed labora-

tory instrument performance in many regards. Noise or

interfering signals on the analog signal input, the voltage

reference or the sampling clock input can easily appear

in the digitized data. To deliver the full performance of

any ADC, the sampling clock input must be driven with a

clean, low jitter signal.

Figure 34 shows a simplified version of a typical ADC

sample clock input. In this case the input pins are labeled

ENC± for Encode while some ADCs label the inputs CLK±

for Clock. The input is composed of a differential limiting

amplifier stage followed by a buffer that directly controls

the ADC’s track and hold stage.

The sample clock input amplifier also benefits from a

fast slewing input signal as the amplifier has noise of its

own. By slewing through the crossover region quickly,

the amplifier noise creates less jitter than if the transition

were slow.

6953 F34

VDD

1.2V

10k

ENC+

ENC–

MEASURING CLOCK JITTER INDIRECTLY USING

ADC SNR

For some applications, integrating a clock generator’s

phase noise within a defined offset frequency range (i.e.,

12kHz to 20MHz) is sufficient to calculate the clock’s

impact on the overall system performance. In these situ-

ations, the RMS jitter can be calculated from a phase

noise measurement.

However, other applications require knowledge of the

clock’s phase noise at frequency offsets that exceed the

capabilities of today’s phase noise analyzers. This limita-

tion makes it difficult to calculate jitter from a phase noise

measurement.

The RMS jitter of an ADC clock source can be indirectly

measured by comparing a jitter dominated SNR measure-

ment to a non-jitter dominated SNR measurement. A jitter

dominated SNR measurement (SNRjitter) is created by

applying a low jitter, high frequency full-scale sinewave to

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