LTC6953

3

Rev 0

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

TABLE OF CONTENTS

Determining Output Divider Values................................................................................................................... 33

Determining Output Digital Delay Values .......................................................................................................... 33

Status Register Programming .......................................................................................................................... 34

Power and FILT Register Programming ............................................................................................................ 34

Output Power-Down Programming................................................................................................................... 34

SYNC and SYSREF Global Modes Programming.............................................................................................. 34

Output Divider, Delay and Function Programming ............................................................................................ 35

Synchronization................................................................................................................................................ 35

Putting the IC Into a Lower Power Mode (Optional) ......................................................................................... 35

Performing a SYSREF Request......................................................................................................................... 35

JESD204B DESIGN Example Using EZSync Multichip...................................................................................... 37

Input Assumptions ........................................................................................................................................... 38

Design Procedure ............................................................................................................................................. 38

Determining Output Modes .............................................................................................................................. 38

Determining Output Divider Values................................................................................................................... 38

Determining Output Digital Delay Values .......................................................................................................... 39

Status Register Programming .......................................................................................................................... 40

Power and FILT Register Programming ............................................................................................................ 40

Output Power-Down Programming................................................................................................................... 41

SYNC and SYSREF Global Modes Programming.............................................................................................. 41

Output Divider, Delay and Function Programming ............................................................................................ 41

Synchronization................................................................................................................................................ 42

Putting the ICs Into a Lower Power Mode ........................................................................................................ 42

Performing a SYSREF Request......................................................................................................................... 42

JESD204B Design Example Using ParallelSync................................................................................................ 44

Supply Bypassing and PCB Layout Guidelines ................................................................................................. 44

ADC Clocking and Jitter Requirements............................................................................................................. 46

Measuring Clock Jitter Indirectly Using ADC SNR ............................................................................................ 48

ADC Sample Clock Input Drive Requirements .................................................................................................. 48

Transmission Lines and Termination................................................................................................................. 49

Using the LTC6953 to Drive Device Clock Inputs ............................................................................................. 49

Using the LTC6953 to Drive DC-Coupled SYSREF Inputs ................................................................................ 49

DC-Coupled SYSREFs (MODEx = 0, 1 or 3)...................................................................................................... 49

Using the LTC6953 to Drive AC-Coupled SYSREF Inputs in Continuous OR Gated Mode ................................ 50

Continuous or Gated SYSREFs (MODEx = 0 or 1) ............................................................................................ 50

Using the LTC6953 to Drive AC-Coupled SYSREF Inputs in Pulsed Mode........................................................ 50

Pulsed SYSREFs (MODEx = 3) ......................................................................................................................... 51

Measuring Differential Spurious Signals Using Single-Ended Test Equipment ................................................. 51

Typical Applications .............................................................................................................52

Package Description ............................................................................................................55

Typical Application ..............................................................................................................56

Related Parts .....................................................................................................................56