LTC6953 datasheet(34/56 Pages) AD

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LTC6953

Rev 0

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

In order to calculate each output’s digital delay value for

this design example, use the following procedure:

1. Delay all of the JESD204B device clocks by half of a

period of the slowest JESD204B device clock. This

delay setting is equal to the divide value of the slowest

device clock because a one code digital delay equals

half of an input cycle. Non-JESD204B clocks (such

as the FPGA management clock) are not included in

this calculation. This delay value defines the desired

SYSREF valid clock edge. In this example, the slowest

JESD204B clock is the FPGA device clock:

DDELSYSvalid = MFPGACLK = 32

DDELADC–CLK = DDELSYSvalid = 32

DDELDAC–CLK = DDELSYSvalid = 32

DDELFPGA–CLK = DDELSYSvalid = 32

2. For each device clock/SYSREF pair, subtract half a

device clock period from DDELSYSvalid to find the

SYSREF delay. This is equivalent to subtracting the

corresponding divide value of the device clock:

DDELADC–SYS = DDELSYSvalid – MADC–CLK

DDELADC–SYS = 32 – 8 = 24

DDELDAC–SYS = DDELSYSvalid – MDAC–CLK

DDELDAC–SYS = 32 – 1 = 31

DDELFPGA–SYS = DDELSYSvalid – MFPGA–CLK

DDELFPGA–SYS = 32 – 32 = 0

Table 14 summarizes the DDEL settings for all outputs.

Table 14. Output DDELx Settings for EZSync Standalone

Design Example

OUTPUT

PURPOSE

DDELx

OUT0

ADC0 SYSREF

OUT1

ADC0 CLK

OUT2

ADC1 SYSREF

OUT3

ADC1 CLK

OUT4

FPGA SYSREF

OUT5

FPGA DEV CLK

OUT6

FPGA MGMT CLK

OUT7

DAC0 SYSREF

OUT8

DAC0 CLK

OUT9

DAC1 SYSREF

OUT10

DAC1 CLK

Now that the output divider and delays have been deter-

mined, the LTC6953 can be programmed.

Status Register Programming

This example will use the STAT pin to alert the system

whenever the LTC6953 generates a fault condition.

Program x[3] = 1 to force the STAT pin high whenever

the VCOOK flag asserts:

Reg01 = h08

Power and FILT Register Programming

For correct operation, all internal blocks should be

enabled. Additionally, the input signal has a sufficient slew

rate and power to not need the FILTV bit:

Reg02 = h00

Output Power-Down Programming

During initial setup and synchronization, all used outputs

and the SRQ circuitry should be set to full power. These

bits will be used later to place the IC in a lower power

mode while waiting for SYSREF requests:

Reg03 = h00

Reg04 = h00

Reg05 = h00

SYNC and SYSREF Global Modes Programming

Bit EZMD controls whether the IC is an EZSync stand-

alone/CONTROLLER (“0”) or FOLLOWER (“1”). Since

this example is an EZSync standalone application, set bit

EZMD to “0”. Bit SRQMD determines if the part is in syn-

chronization mode (“0”) or SYSREF request mode (“1”).

SYSCT programs the number of pulses for any output in

pulsed SYSREF mode (# pulses = 2SYSCT, so SYSCT = 2

to achieve four pulses for this example). Using this infor-

mation, register h0B can be programmed:

Reg0B = h04

Note that the SSRQ bit will remain “0” for now, but will be

used later during the synchronization and SYSREF request

procedures. Also, the EZS_SRQ± pins should be grounded

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