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LTC6953 数据表(PDF) 2 Page - Analog Devices |
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LTC6953 数据表(HTML) 2 Page - Analog Devices |
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2 / 56 page ![]() LTC6953 2 Rev 0 For more information www.analog.com Preliminary Technical Data Advance Product Information Subject to Change Rev PrA TABLE OF CONTENTS Features ............................................................................................................................ 1 Applications ....................................................................................................................... 1 Typical Application ............................................................................................................... 1 Description......................................................................................................................... 1 Absolute Maximum Ratings..................................................................................................... 4 Electrical Characteristics ........................................................................................................ 4 Pin Configuration ................................................................................................................. 4 Typical Performance Characteristics .......................................................................................... 8 Pin Functions .....................................................................................................................11 Block Diagram....................................................................................................................12 Timing Diagrams ................................................................................................................13 Operation..........................................................................................................................14 Input Buffer ...................................................................................................................................................... 14 Input Peak Detector .......................................................................................................................................... 14 Output Dividers (M0 to M10)............................................................................................................................ 14 Digital Output Delays (DDEL0 to DDEL10) ....................................................................................................... 15 Analog Output Delays (ADEL0 to ADEL10) ....................................................................................................... 15 CML Output Buffers (OUT0 to OUT10) ............................................................................................................. 15 Output Synchronization and SYSREF Generation ............................................................................................. 16 EZS_SRQ Input Buffer ...................................................................................................................................... 16 Synchronization Overview ................................................................................................................................ 16 SYSREF Generation Overview .......................................................................................................................... 17 Multichip Synchronization and SYSREF Generation ......................................................................................... 17 EZSync Multichip.............................................................................................................................................. 19 ParallelSync...................................................................................................................................................... 20 Power Savings in SYSREF Generation Mode.................................................................................................... 21 SERIAL PORT ................................................................................................................................................... 23 Communication Sequence................................................................................................................................ 23 Single Byte Transfers ........................................................................................................................................ 23 Multiple Byte Transfers ..................................................................................................................................... 24 Multidrop Configuration ................................................................................................................................... 25 Serial Port Registers......................................................................................................................................... 25 STAT Output ..................................................................................................................................................... 28 Block Power-Down Control............................................................................................................................... 28 Applications Information .......................................................................................................29 Introduction...................................................................................................................................................... 29 Output Frequency ............................................................................................................................................. 29 Digital and Analog Output Delays ..................................................................................................................... 29 Input Buffer ...................................................................................................................................................... 30 EZS_SRQ Input................................................................................................................................................. 31 JESD204B Design Example Using EZSync Standalone..................................................................................... 32 Input Assumptions ........................................................................................................................................... 32 Design Procedure ............................................................................................................................................. 32 Determining Output Modes .............................................................................................................................. 33 |
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