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LTC6953 数据表(PDF) 22 Page - Analog Devices

部件名 LTC6953
功能描述  Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B Support
PDF  56 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

LTC6953 数据表(HTML) 22 Page - Analog Devices

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LTC6953
22
Rev 0
For more information www.analog.com
Preliminary Technical Data
Advance Product Information Subject to Change
Rev PrA
Figure 10. Flowchart to Determine the Best Synchronization Protocol for a Given Application
START
INPUTS:
TP = TOTAL NUMBER OF JESD DEVICE CLOCK/SYSREF PAIRS
LNP = NUMBER OF JESD PAIRS REQUIRING LOW
NOISE (< 100fs) DEVICE CLOCKS
TS = TOTAL NUMBER OF STAND ALONE CLOCK SIGNALS
LNS = NUMBER OF REQUIRED LOW
NOISE (< 100fs) STAND ALONE CLOCKS
T = 2TP + TS
INPUTS:
T = TOTAL NUMBER OF CLOCK SIGNALS
LNS = NUMBER OF REQUIRED LOW
NOISE (< 100fs) CLOCKS
JESD204B
APPLICATION?
NOTE: CEILING() FUNCTION MEANS ROUND
UP TO NEXT HIGHEST INTEGER.
YES
NO
T ≤ 11?
NO
NO
YES
T ≤ 11?
YES
USE EZSync
STANDALONE
USE EZSync MULTICHIP
WITH REQUEST PASS-
THROUGH (1 CONTROLLER
AND P FOLLOWERS)
USE ParallelSync WITH
LTC6953 REFERENCE
DISTRIBUTION
(P PARALLEL PARTS)
T ≤ 56
AND TP ≤ 25
AND LNS
≤ 11 – P2 – 2LNP
AND LNP
≤ 5 – P?
NO
NO
YES
T ≤ 56
AND LNS
≤ 11 – 2P?
YES
NO
NO
YES
YES
NO
NO
YES
YES
T ≤ 25
AND
TP ≤ 25?
T ≤ 121
AND
LNS ≤ 11 – P?
T ≤ 121
AND TP ≤ 55
AND LNS
≤ 11 – P – 2LNP
AND LNP
≤ (55 – TP)/9?
T ≤ 55?
6953 F10
USE STANDARD EZSync
MULTICHIP
(1 CONTROLLER
AND P FOLLOWERS)
USE STANDARD
ParallelSync
MULTICHIP
(P PARALLEL PARTS)
P
= CEILING MAX
T
11
,
TP
5




P
= CEILING MAX
T – 11
9
,
TP – 5
4




P
= CEILING
T – 11
9


P
= CEILING
T – 11
10


P
= CEILING MAX
T – 11
10
,
TP – 5.5
4.5




P
= CEILING MAX
T
11
,
TP
5




P
= CEILING
T
11


P
= CEILING
T
11


OPERATION



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