LTC6953 datasheet(39/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

known, which leaves the two CONTROLLER outputs that

drive the FOLLOWER to be described. Since OUT8 of the

CONTROLLER drives the FOLLOWER input, its frequency

must be equal to or larger than, the highest FOLLOWER

frequency. Therefore:

fCONT-OUT8 = 4000MHz

Additionally, when using the software-controlled

EZSync configuration in a JESD204B application, the

CONTROLLER output which drives the FOLLOWER’s

EZS_SRQ inputs should be set to the same frequency as

the SYSREF frequency (or the slowest SYSREF frequency

if multiple SYSREF periods are used).

fCONT–OUT9 = 12.5MHz

Now that all frequencies are known, use Equation 4 to

determine the output divider values. The results are

shown in Table 17.

Table 17. Output Divide Settings for EZSync Multichip

Design Example

IC OUTPUT

PURPOSE

FREQUENCY

(MHZ)

DIVIDE

VALUE (Mx)

OUT0

ADC0 SYSREF

12.5

320

OUT1

ADC0 CLK

500

OUT2

ADC1 SYSREF

12.5

320

OUT3

ADC1 CLK

500

OUT4

ADC2 SYSREF

12.5

320

OUT5

ADC2 CLK

500

OUT6

ADC3 SYSREF

12.5

320

OUT7

ADC3 CLK

500

OUT8

To FOLLOWER IN±

4000

OUT9

FOLLOWER EZS_SRQ

12.5

320

OUT10

FPGA MGMT CLK

100

OUT0

Unused

N/A

OUT1

FPGA SYSREF

12.5

320

OUT2

FPGA DEV CLK

125

OUT3

DAC0 SYSREF

12.5

320

OUT4

DAC0 CLK

4000

OUT5

DAC1 SYSREF

12.5

320

OUT6

DAC1 CLK

4000

OUT7

DAC2 SYSREF

12.5

320

OUT8

DAC2 CLK

4000

OUT9

DAC3 SYSREF

12.5

320

OUT10

DAC3 CLK

4000

Determining Output Digital Delay Values

The output digital delay is used to control phase relation-

ships between outputs. The minimum delay step is ½ of

a period of the input signal. For this design example, the

digital delay is used to place each device’s SYSREF signal

edges into a known phase relationship to its correspond-

ing device clock, optimized for the set-up (ts) and hold

time (th) requirements for that device. Assume that the

optimum SYSREF edge location for each device occurs

on the first falling clock edge before the desired SYSREF

valid rising clock edge. Refer to Figure 23 for an example.

For EZSync multichip synchronization, the CONTROLLER

output which drives the FOLLOWER input (follower-driver)

must output seven pulses before the FOLLOWER outputs

begin. This means that any CONTROLLER outputs which

should be aligned with the FOLLOWER outputs (follower-

synchronous) must be delayed by the same amount of

time as the seven pulses, leading to a delay offset for

each of these follower-synchronous outputs (DDELFS-OS):

DDELFS–OS = 14 • MFD + DDELFD

(8)

where MFD and DDELFD are the divider value and digital

delay value, respectively, of the follower-driver. In most

applications, DDELFD will be set to 0.

In order to calculate each output’s delay value for this

design example, use the following procedure:

1. Delay all of the JESD204B device clocks by half of a

period of the slowest JESD204B device clock. This

delay setting is equal to the divide value of the slow-

est device clock because a one code digital delay

equals half of an input clock cycle. Non-JESD204B

clocks (such as the FPGA management clock) are not

included in this calculation. This delay value defines

the desired SYSREF valid clock edge. In this example,

the slowest JESD204B clock is the FPGA device clock:

DDELSYSvalid = MFPGACLK = 32

DDELADC–CLK´ = DDELSYSvalid = 32

DDELDAC–CLK´ = DDELSYSvalid = 32

DDELFPGA–CLK´ = DDELSYSvalid = 32

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