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LTC6953 数据表(PDF) 25 Page - Analog Devices

部件名 LTC6953
功能描述  Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B Support
PDF  56 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

LTC6953 数据表(HTML) 25 Page - Analog Devices

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LTC6953
25
Rev 0
For more information www.analog.com
Preliminary Technical Data
Advance Product Information Subject to Change
Rev PrA
continues sending bytes destined for subsequent regis-
ters. Byte 1’s address is ADDRX + 1, Byte 2’s address
is ADDRX + 2, and so on. If the register address pointer
attempts to increment past 56 (h38), it is automatically
reset to 0.
An example of an auto-increment read from the part is
shown in Figure 17. The first byte of the burst sent from
the serial bus master on SDI contains the destination
register address (ADDRX) and an LSB of “1” indicating a
read. Once the LTC6953 detects a read burst, it takes SDO
out of the Hi-Z condition and sends data bytes sequen-
tially, beginning with data from register ADDRX. The part
ignores all other data on SDI until the end of the burst.
Multidrop Configuration
Several LTC6953s may share the serial bus. In this mul-
tidrop configuration, SCLK, SDI, and SDO are common
between all parts. The serial bus master must use a sepa-
rate CS for each part and ensure that only one device has
CS asserted at any time. It is recommended to attach a
OPERATION
Figure 16. Serial Port Auto-Increment Write
Figure 17. Serial Port Auto-Increment Read
ADDRX + Wr
Hi-Z
MASTER–CS
MASTER–SDI
LTC6953–SDO
BYTE X
BYTE X + 1
BYTE X + 2
6953 F16
ADDRX + Rd
DON’T CARE
Hi-Z
Hi-Z
MASTER–CS
MASTER–SDI
LTC6953–SDO
6953 F17
BYTE X
BYTE X + 1
BYTE X + 2
high value resistor to SDO to ensure the line returns to a
known level during Hi-Z states.
Serial Port Registers
The memory map of the LTC6953 is found in Table 10,
with detailed bit descriptions found in Table 11. The reg-
ister address shown in hexadecimal format under the
“ADDR” column is used to specify each register. Each
register is denoted as either read-only (R) or read-write
(R/W). The register’s default value on device power-up or
after a reset is shown at the right.
The read-only register at address h00 is used to determine
different status flags. These flags may be instantly output
on the STAT pin by configuring register h01. See STAT
Output section for more information.
The register at address h38 is a read-only byte for device
identification.



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