LTC6953 datasheet(46/56 Pages) AD

46 / 56 page

LTC6953

Rev 0

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

ADC CLOCKING AND JITTER REQUIREMENTS

Adding noise directly to a clean signal clearly reduces its

signal to noise ratio (SNR). In data acquisition applica-

tions, digitizing a clean signal with a noisy clock signal

also degrades the SNR. This issue is best explained in

the time domain using jitter instead of phase noise. For

this discussion, assume that the jitter is white (flat with

frequency) and of Gaussian distribution.

Figure 31 shows a sine wave signal entering a typical data

acquisition circuit composed of an ADC, an input signal

amplifier and a sampling clock. Also shown are three sig-

nal sampling scenarios for sampling the sine wave at its

zero crossing.

In the first scenario, a perfect sine wave input is buffered

by a noiseless amplifier to drive the ADC. Sampling is per-

formed by a perfect, zero jitter clock. Without any added

noise or sampling clock jitter, the ADC’s digitized output

value is very clearly determined and perfectly repeatable

from cycle to cycle.

In the second scenario, a perfect sine wave input is buff-

ered by a noisy amplifier to drive the ADC. Sampling is

performed by a perfect, zero jitter clock. The added noise

results in an uncertainty in the digitized value, causing an

error term which degrades the SNR. The degraded SNR in

this scenario, from adding noise to the signal, is expected.

In the third scenario, a perfect sine wave input is buffered

by a noiseless amplifier to drive the ADC. Sampling is

performed by a clock signal with added jitter. Note that

as the signal is slewing, the jitter of the clock signal leads

to an uncertainty in the digitized value and an error term

just as in the previous scenario. Again, this error term

degrades the SNR.

A real-world system will have both additive amplifier noise

and sample clock jitter. Once the signal is digitized, deter-

mining the root cause of any SNR degradation—amplifier

noise or sampling clock jitter—is essentially impossible.

Degradation of the SNR due to sample clock jitter only

occurs if the analog input signal is slewing. If the analog

input signal is stationary (DC) then it does not matter

when in time the sampling occurs. Additionally, a faster

slewing input signal yields a greater error (more noise)

than a slower slewing input signal.

Figure 30. PCB Top Metal Layer Pin and Exposed Ground Pad Design. Pin 41 is Signal

Ground and Connected Directly to the Exposed Pad Metal

6953 F30

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