LTC6953 datasheet(49/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Figure 35. Far-End Transmission Line Termination

(Z0 = 50Ω)

As shown in Figure 34, the ADC’s sample clock input

is typically differential, with a differential sampling clock

delivering the best performance. Figure 34 also shows

the sample clock input having a different common mode

input voltage than the LTC6953’s CML outputs. Most ADC

applications will require AC-coupling to convert between

the two common mode voltages.

TRANSMISSION LINES AND TERMINATION

Interconnection of high speed signaling with fast rise

and fall times requires the use of transmission lines with

properly matched termination. The transmission lines

may be stripline, microstrip or any other design topol-

ogy. A detailed discussion of transmission line design

is beyond the scope of this data sheet. Any mismatch

between the transmission line’s characteristic impedance

and the terminating impedance results in a portion of the

signal reflecting back toward the other end of the trans-

mission line. In the extreme case of an open or short

circuit termination, all of the signal is reflected back. This

signal reflection leads to overshoot and ringing on the

waveform. Figure 35 shows the preferred method of far-

end termination of the transmission line.

6953 F35

100Ω

USING THE LTC6953 TO DRIVE DC-COUPLED

SYSREF INPUTS

For JESD204B applications, the SYSREF signal would

ideally be DC-coupled from the LTC6953 to the data con-

verter or FPGA as shown in Figure 37. This is possible for

receiver devices that can accept a 2.3V common mode

input signal. Note that some receiver devices have the

100Ω termination resistor internal to the part, in which

case the external 100Ω resistor is unnecessary.

Figure 36. OUTx CML Connections to Device Clock

Inputs (Z0 = 50Ω)

100Ω

OUTx +

OUTx –

6953 F36

LTC6953

ADC, DAC,

OR FPGA

OUTx +

OUTx –

LTC6953

DEVICES THAT CAN

ACCEPT A 2.3V

COMMON MODE

SIGNAL

AC-COUPLED INTO

LVDS OR DEVICES

REQUIRING A SELF-

BIASED INPUT

CLK+

CLK–

ADC, DAC,

OR FPGA

CLK+

CLK–

Figure 37. OUTx CML DC-Coupled Connections to

SYSREF Inputs

100Ω

OUTx +

OUTx –

6953 F37

LTC6953

ADC, DAC,

OR FPGA

DEVICES THAT CAN

ACCEPT A 2.3V

COMMON MODE

SIGNAL

SYSREF +

SYSREF –

USING THE LTC6953 TO DRIVE DEVICE CLOCK

INPUTS

The LTC6953’s CML outputs are designed to interface

with standard CML or LVPECL devices while driving trans-

mission lines with far-end termination. Figure 36 shows

DC-coupled and AC-coupled output configurations for the

CML outputs. Note that some receiver devices have the

100Ω termination resistor internal to the part, in which

case the external 100Ω resistor is unnecessary.

Use the following procedure to achieve correct JESD204B

SYSREF behavior for DC-coupled SYSREFs in any mode.

These methods assume that the SYSREF outputs have

already been synchronized and that the SYSREF output

drivers have been disabled for power savings (PDx = 2).

DC-Coupled SYSREFs (MODEx = 0, 1 or 3)

1. Enable the LTC6953 SYSREF output drivers by setting

PDx = 0 and set SRQMD = 1.

2. Set the receiver device to accept SYSREFs.

3. Set SSRQ or the EZS_SRQ inputs to “1” for at least

1ms, then set back to “0”.

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