LTC6953 datasheet(41/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Additionally, the input signal has a sufficient slew rate

and power to not need the FILTV bit:

CONTROLLER Reg02 = h00

FOLLOWER Reg02 = h00

Output Power-Down Programming

During initial setup and synchronization, all used outputs

should be set to full power. These bits will be used later

to place the ICs in a lower power mode while waiting for

SYSREF requests:

CONTROLLER Reg03 = h00

CONTROLLER Reg04 = h00

CONTROLLER Reg05 = h00

FOLLOWER Reg03 = h03

FOLLOWER Reg04 = h00

FOLLOWER Reg05 = h00

SYNC and SYSREF Global Modes Programming

Bit EZMD controls whether the IC is an EZSync standalone/

CONTROLLER (“0”) or FOLLOWER (“1”). Bit SRQMD

determines if the part is in synchronization mode (“0”)

or SYSREF request mode (“1”). SYSCT programs the

number of pulses for any output in pulsed SYSREF mode

(# pulses = 2SYSCT, so SYSCT = 2 to achieve four pulses

for this example). Using this information, register h0B

for CONTROLLER and FOLLOWER can be programmed:

CONTROLLER Reg0B = h04

FOLLOWER Reg0B = h14

Note that the SSRQ bits will remain “0” for now, but will

be used later during the synchronization and SYSREF

request procedures.

Output Divider, Delay and Function Programming

Four registers for each output allow the outputs to be

configured independently of each other. The first regis-

ter controls the output divide ratio through two control

words, MPx and MDx, as described in Equation 1. The

second register contains the control modes and the most

significant bits of the digital delay control word. The third

word, and the fourth register is the analog delay control.

Both the analog delay and the output invert (OINVx) bits

can be used to correct PC board layout issues such as

mismatched trace lengths and differential signal cross-

overs, respectively. Note that the use of analog delay on

clock signals will degrade jitter performance. For this

example, assume the PC board is laid out in an ideal man-

ner and no output inversions or analog delays are needed.

With this information, all of registers h0C through h37 for

both CONTROLLER and FOLLOWER can be programmed

to the values in Table 19 and Table 20, calculated using

the information in Table 24, Table 25 (with Equation 1),

and Table 26.

Table 19. CONTROLLER Output Register Settings for EZSync

Multichip Design Example

ADDR

VALUE

ADDR

VALUE

ADDR

VALUE

h0C

h9C

h1C

h9C

h2C

h00

h0D

hE0

h1D

hE0

h2D

h80

h0E

h26

h1E

h26

h2E

h00

h0F

h00

h1F

h00

h2F

h00

h10

h38

h20

h38

h30

h9C

h11

h80

h21

h80

h31

hC0

h12

h2E

h22

h2E

h32

h2D

h13

h00

h23

h00

h33

h00

h14

h9C

h24

h9C

h34

h99

h15

hE0

h25

hE0

h35

h00

h16

h26

h36

h00

h17

h00

h27

h00

h37

h00

h18

h38

h28

h38

h19

h80

h29

h80

h1A

h2E

h2A

h2E

h1B

h00

h2B

h00

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