LTC6953 datasheet(47/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Figure 31. A Typical Data Acquisition Circuit Showing the Sampling Error Effects of a Noisy Amplifier and a Jittery Sampling Clock

Figure 32. Fast and Slow Sine Wave Signals

Sampled with a Jittery Clock

6953 F32

∆V = VERROR(SLOW)

∆V = VERROR(FAST)

FAST

SINE WAVE

SLOW

SINE WAVE

Figure 32 demonstrates this effect. Note how much larger

the error term is with the fast slewing signal than with the

slow slewing signal. To maintain the data converter’s SNR

performance, digitization of high input frequency signals

requires a clock with much less jitter than applications

with lower frequency input signals.

6953 F31

SINE WAVE

INPUT SIGNAL WITH

NOISELESS AMP

SAMPLING CLOCK WITH ADDED JITTER

∆V = VERROR

SINE WAVE

INPUT SIGNAL WITH

NOISY AMP

SINE WAVE

INPUT SIGNAL

PERFECT SAMPLING CLOCK

∆V = VERROR

SINE WAVE

INPUT SIGNAL WITH

NOISELESS AMP

PERFECT SAMPLING CLOCK

VSAMPLE

SAMPLING CLOCK

BITS

ADC

AMP

It is important to note that the frequency of the analog

input signal determines the sample clock’s jitter require-

ment. The actual sample clock frequency does not matter.

Many ADC applications that undersample high frequency

signals have especially challenging sample clock jitter

requirements.

The previous discussion was useful for gaining an intuitive

feel for the SNR degradation due to sampling clock jitter.

Quantitatively, the actual sample clock jitter requirement

for a given application is calculated as:

t J(TOTAL) =

–SNRdB

2 • π • fSIG

(9)

Where fSIG is the highest frequency signal to be digitized

expressed in Hz, SNRdB is the SNR requirement in deci-

bels and tJ(TOTAL) is the total RMS jitter in seconds. The

total jitter is the RMS sum of the ADC’s aperture jitter and

the sample clock jitter calculated as:

t J(TOTAL) = t J(CLK)2 + tJ(ADC)2

(10)

Alternatively, for a given total jitter, the attainable SNR is

calculated as follows:

SNR dB = –20log10(2 • π • fSIG • tJ(TOTAL))

(11)

These calculations assume a full-scale sine wave input

signal. If the input signal is a complex, modulated signal

with a moderate crest factor, the peak slew rate of the

signal may be lower and the sample clock jitter require-

ment may be relaxed.

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