LTC6953 datasheet(50/56 Pages) AD

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LTC6953

Rev 0

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Figure 39. OUTx CML AC Coupled Connections to SYSREF Inputs

for Pulsed Mode Operation

Figure 38. OUTx CML AC Coupled Connections to SYSREF Inputs

for Continuous or Gated Mode Operation

4. After the SYSREFs have been accepted by the receiver

device, set the device to stop accepting SYSREFs.

5. Disable the LTC6953 SYSREF output drivers by set-

ting PDx = 2 and set SRQMD = 0.

USING THE LTC6953 TO DRIVE AC-COUPLED SYSREF

INPUTS IN CONTINUOUS OR GATED MODE

Some converters cannot accept a 2.3V common mode CML

signal. In this situation, the SYSREF must be AC-coupled.

AC-coupling complicates the usage of SYSREF since it is

generally not continuously operational, leading to long

settling time requirements before a SYSREF is requested.

However, AC-coupling on SYSREF can be accomplished

by using the connections shown in Figure 38 for continu-

ous or gated SYSREF pulses (MODEx = 0 or 1). Note that

some receiver devices have the 100Ω termination resis-

tor internal to the part, in which case the external 100Ω

resistor is unnecessary for continuous or gated SYSREFs.

Continuous or Gated SYSREFs (MODEx = 0 or 1)

1. Enable the LTC6953 SYSREF output drivers by setting

PDx = 0 and set SRQMD = 1.

2. If gated SYSREFs (MODEx = 1) are being used, set

SSRQ or the EZS_SRQ inputs to “1”.

3. Wait for a settling period of at least tsettleC.

4. Set the receiver device to accept SYSREFs.

5. After the SYSREFs have been accepted by the receiver

device, set the device to stop accepting SYSREFs.

6. If gated SYSREFs (MODEx = 1) are being used, set

SSRQ or the EZS_SRQ inputs to “0”.

7. Disable the LTC6953 SYSREF output drivers by set-

ting PDx = 2 and set SRQMD = 0.

USING THE LTC6953 TO DRIVE AC-COUPLED SYSREF

INPUTS IN PULSED MODE

If AC-coupling is required for pulsed SYSREF applications

(MODEx = 3), the connections shown in Figure 39 can be

used. Note that some receiver devices have the 100Ω ter-

mination resistor internal to the part. In this situation, the

use of AC-coupled, pulsed SYSREFs is not recommended.

Settling time for continuous or gated SYSREF connec-

tions is determined by the AC-coupling capacitors (CAC),

and both the differential and common mode input resis-

tances of the receiver device (RDIFF and RCM):

tsettleC ≅ 10 • 2RCM +

RDIFF

⎛

⎝

⎜

⎞

⎠

⎟ • C AC

Use the following procedure to achieve correct JESD204B

SYSREF behavior for AC-coupled continuous or gated

SYSREFs.

These methods assume that the SYSREF outputs have

already been synchronized and that the SYSREF output

drivers have been disabled for power savings (PDx = 2).

100Ω

CAC

RDIFF /2

RCM

6953 F38

OUTx +

OUTx –

LTC6953

ADC, DAC, OR FPGA

SYSREF +

SYSREF –

VCM

RDIFF /2

CAC

RDIFF /2

RCM

100Ω

CAC

ADC, DAC, OR FPGA

SYSREF

SYSREF –

VCM

OUTx +

OUTx –

LTC6953

VDD

6953 F39

The purpose of R1 and R2 in Figure 39 is to force an

offset at the SYSREF inputs equivalent to a CML logic

“0” when the SYSREF output is not active. The resistors’

values are determined by the supply voltage (VDD) and

the receiver device’s input common mode voltage (VCM)

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