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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

The LTC6953 is a high performance multioutput clock

distributor that operates up to 4.5GHz. Utilizing Analog

Devices’s proprietary EZSync and ParallelSync standards,

users of the LTC6953 and its companion part LTC6952

can synchronize clocks across multiple outputs and mul-

tiple chips. The device is able to achieve superior addi-

tive integrated jitter performance by way of its excellent

output noise floor. For JESD204B subclass 1 applications,

the LTC6953 also provides several convenient methods

to generate SYSREF pulses.

INPUT BUFFER

The LTC6953’s input buffer provides a flexible interface to

either differential or single-ended frequency sources. The

inputs are self-biased, and AC-coupling is recommended

for applications using external VCO/VCXO/VCSOs.

However, the input can also be driven DC-coupled by

LVPECL, CML or any other driver type within the input’s

specified common mode range. See the Applications

Information section for more information on common

input interface configurations, noting that the LTC6953’s

input buffer has an internal differential resistance of 250Ω

as shown in Figure 1.

phase noise performance will be achieved by enabling the

internal broadband noise filtering circuit within the input

buffer. This is accomplished by asserting the configura-

tion bit FILTV in serial port register h02. Note that setting

FILTV = 1 when the slew rate of the input is greater than

2V/ns will degrade the overall PLL-phase noise perfor-

mance. See Table 1 for recommended settings of FILTV.

Table 1. FILTV Programming

FILTV

SLEW RATE OF INPUT

< 2V/ns

≥ 2V/ns

Input Peak Detector

An input peak detection circuit on the IN± inputs detects

the presence of an input signal and provides the VCOOK

and VCOOK status flags available through both the STAT

output and serial port register h00. VCOOK is the logical

inverse of VCOOK. The circuit has hysteresis to prevent

the VCOOK flag from chattering at the detection thresh-

old. The peak detector may be powered-down using the

PDVCOPK bit found in register h02.

The peak detector approximates an RMS detector, there-

fore sine and square wave inputs will give different detec-

tion thresholds by a factor of 4/π. See Table 2 for VCOOK

detection values.

Table 2. VCOOK, VCOOK Status Output vs Input Amplitude

VCOOK

SINE WAVE fIN

SQUARE WAVE fIN

≥ 350mVP-P

≥ 275mVP-P

< 100mVP-P

< 75mVP-P

OUTPUT DIVIDERS (M0 TO M10)

The eleven independent, identical output dividers are

driven directly from the input buffer. They divide the

input frequency fIN by the divide value Mx to produce a

50% duty cycle output signal at frequency fOUTx. The Mx

value is set by the MPx[4:0] and the MDx[2:0] bits using

Equation 1:

= MPx + 1

(

) • 2MDx

(1)

For proper operation, MDx must be 0 if Mx is less than

or equal to 32.

Figure 1. Simplified Input Interface Schematic

VIN

FILTV

BIAS

125Ω

935Ω

IN–

IN+

2.1V

125Ω

6953 F01

The maximum input frequency for the input buffer is

4.5GHz, and the maximum amplitude is 1.6VP-P. It is

also important that the IN± input signal be low noise and

have a slew rate of at least 100V/µs, although better per-

formance will be achieved with a higher slew rate. For

applications with input slew rates less than 2V/ns, better

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