LTC6953 datasheet(35/56 Pages) AD

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LTC6953

Rev 0

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

because the synchronization and SYSREF requests will be

accomplished through software control of the SSRQ bit.

Output Divider, Delay and Function Programming

Four registers for each output allow the outputs to be

configured independently of each other. The first regis-

ter controls the output divide ratio through two control

words, MPx and MDx, as described in Equation 1.

The second register contains the control modes and the

most significant bits of the digital delay control word.

The third register contains the remainder of the digital

delay control word, and the fourth register is the analog

delay control.

Both the analog delay and the output invert (OINVx) bits

can be used to correct PC board layout issues such as mis-

matched trace lengths and differential signal crossovers,

respectively. Note that the use of analog delay on clock

signals will degrade jitter performance. For this example,

assume the PC board is laid out in an ideal manner and

no output inversions or analog delays are needed. With

this information, all of registers h0C through h37 can be

programmed to the values in Table 15, calculated using

the information in Tables 20, 21 (with Equation 1) and 22.

Table 15. Output Register Settings for EZSync Standalone Design

Example

ADDR

VALUE

ADDR

VALUE

ADDR

VALUE

h0C

h9C

h1C

h9C

h2C

h00

h0D

hE0

h1D

hE0

h2D

h80

h0E

h18

h1E

h00

h2E

h20

h0F

h00

h1F

h00

h2F

h00

h10

h38

h20

hF8

h30

h9C

h11

h80

h21

h80

h31

hE0

h12

h20

h22

h20

h32

h1F

h13

h00

h23

h00

h33

h00

h14

h9C

h24

h99

h34

h00

h15

hE0

h25

h00

h35

h80

h16

h18

h26

h00

h36

h20

h17

h00

h27

h00

h37

h00

h18

h38

h28

h9C

h19

h80

h29

hE0

h1A

h20

h2A

h1F

h1B

h00

h2B

h00

Synchronization

The outputs in this example are now running at the

desired frequency, but have random phase relationships

with each other. Synchronization forces the outputs to run

at known and repeatable phases and can be achieved in

this example either externally, by driving the EZS_SRQ±

pins or internally, with the SSRQ bit in Reg0B. Since the

part was just programmed, set the SSRQ bit to “1” and

hold the EZS_SRQ± pins low:

Reg0B = h05

After waiting a minimum of 1ms, set SSRQ to “0”:

Reg0B = h04

Once the internal synchronization process completes, the

outputs will be aligned as shown in Figure 24. Note that

the internal divider behavior for the muted SYSREF out-

puts is shown as well as the actual outputs to demonstrate

the phase alignment following synchronization.

Putting the IC Into a Lower Power Mode (Optional)

If desired, the LTC6953 can be placed into a lower power

mode while awaiting a SYSREF request. This is achieved

by setting PDx = 2 for all SYSREF-defined outputs. This

powers down the output driver circuitry but leaves the

internal divider running and in the correct phase relation-

ship to the clocks.

Performing a SYSREF Request

To produce SYSREF pulses, write a “1” to SRQMD and

take the LTC6953 out of low power mode (if used) by

writing all the SYSREF output PDx bits to “0”. Wait 50µs

to allow circuitry to power up. Send the SYSREF request

by writing a “1” to the SSRQ bit in Reg0B:

Reg0B = h05

After waiting a minimum of 1ms, set SSRQ to “0”:

Reg0B = h04

Place the IC back into low power mode if desired by writ-

ing a “0” to SRQMD and setting PDx = 2 for all SYSREF

defined outputs. After the rising edge of the SYSREF

request, the SYSREF outputs will pulse four times and

then return to a “0” state as shown in Figure 25.

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