LTC6953 datasheet(1/56 Pages) AD

部件名	LTC6953

功能描述	Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B Support

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制造商	AD [Analog Devices]

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LTC6953

1

Rev 0

For more information www.analog.com

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

TYPICAL APPLICATION

FEATURES

DESCRIPTION

Ultralow Jitter, 4.5GHz Clock Distributor

with 11 Outputs and JESD204B Support

The LTC®6953 is a high performance, ultralow jitter,

JESD204B clock distribution IC. The LTC6953’s eleven

outputs can be configured as up to five JESD204B sub-

class 1 device clock/SYSREF pairs plus one general

purpose output, or simply eleven general purpose clock

outputs for non-JESD204B applications. Each output has

its own individually programmable frequency divider and

output driver. All outputs can also be synchronized and

set to precise phase alignment using individual coarse half

cycle digital delays and fine analog time delays.

For applications requiring more than eleven total out-

puts, multiple LTC6953s can be connected together with

LTC6952s and LTC6955s using the EZSync or ParallelSync

synchronization protocols.

Low Cost, Eleven Output JESD204B Solution

APPLICATIONS

n

JESD204B, Subclass 1 SYSREF Signal Generation

n

Additive Output Jitter < 6fsRMS (Integration

BW = 12kHz to 20MHz, f = 4.5GHz)

n

Additive Output Jitter 65fsRMS (ADC SNR Method)

n

EZSync™, ParallelSync™ Multichip Synchronization

n

Eleven Independent, Low Noise Outputs with

Programmable Coarse Digital and Fine Analog Delays

n

Flexible Outputs Can Serve as Either a Device Clock

or SYSREF Signal

n

LTC6952Wizard Software Design Tool Support

n

–40°C to 125°C Operating Junction Temperature Range

n

High Performance Data Converter Clocking

n

Wireless Infrastructure

n

Test and Measurement

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. patents, including 8319551 and 8819472.

Cumulative Phase Noise,

LTC6946 Driving LTC6953

4.5GHz

500MHz

OFFSET FREQUENCY (Hz)

1k

10k

100k

1M

10M 40M

–170

–160

–150

–140

–130

–120

–110

–100

6953 TAO1b

TOTAL COMBINED

RMS JITTER = 150fs

LTC6946 RMS JITTER = 135fs

LTC6963 RMS JITTER = 65fs

EQUIVALENT ADC SNR METHOD

49.9Ω

1µF

100Ω

1µF

160Ω

68nH

1µF

100pF

30.9Ω

57nF

4.7nF

2.2µF

15Ω

0.1µF

100Ω

CRYSTEK

CCHD-575-25-100

100MHz REF OSC

REF+

REF –

CP

VVCO

+ VCP+ VREF0+ VREF+ VD+

VIN

+ VREF+ VD+ VOUT+

VRF

+

CMA

CMB

CMC

TB

TUNE

MUTE

BB

RF+

RF –

REFO

3.3V

5V

TO SYNC OUTPUTS:

TOGGLE LTC6953 SSYNC

REGISTER BIT

CS

SCLK

SDI

SDO

STAT

LTC6946-2

IN+

IN–

3.3V

LTC6953

3.3V

EZS_SRQ+

EZS_SRQ–

OUTx+

OUTx–

6953 TA01a

15.625MHz ADC SYSREF

500MHz ADC CLOCK

4.5GHz DAC CLOCK

125MHz FPGA CLOCK

OUT10±

OUT6±

OUT7±

OUT8±

OUT9±

OUT0±

OUT1±

OUT2±

OUT3±

OUT4±

OUT5±

15.625MHz ADC SYSREF

15.625MHz FPGA SYSREF

15.625MHz DAC SYSREF

OUTPUT

TERMINATION DETAIL

CS

SCLK

SDI

SDO

STAT

SPI BUS

REGISTER VALUES:

LTC6952Wizard FILE: LTC6946 LTC6953 EZSync

PLLWizard™ FILE: LTC6946 LTC6953 EZSync

SPI BUS

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类似零件编号 - LTC6953

制造商	部件名	数据表	功能描述
Linear Technology	LTC695	141Kb / 16P	Microprocessor Supervisory Circuits
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类似说明 - LTC6953

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Analog Devices	LTC6952	949Kb / 80P	Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B Support
Texas Instruments	LMK04828-EP	2Mb / 102P	Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner