LTC6953 datasheet(33/56 Pages) AD

33 / 56 page

LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Note that synchronization MUST be performed before a

SYSREF request. The synchronization must be repeated

only if the divider setting is changed or if the divider is

powered down.

Determining Output Modes

All outputs can be programmed as clocks (MODEx = 0),

SYSREFs (MODEx = 1 or 3) or SYNC/SRQ pass-through

outputs (MODEx = 2) using each output’s individual

MODEx bits as described in Table 5 and Table 6. Any out-

put can also be programmed to ignore SYNC and SYSREF

requests by setting that output’s corresponding SRQENx

bit to “0”. Noting that this design example calls for pulsed

SYSREFs (MODEx = 3) and that the FPGA management

clock should always be free running (SRQENx = 0),

Table 12 summarizes each output’s mode settings.

Table 12. Output Mode Settings for EZSync Standalone

Design Example

OUTPUT

PURPOSE

SRQENx

MODEx

PDx

OUT0

ADC0 SYSREF

OUT1

ADC0 CLK

OUT2

ADC1 SYSREF

OUT3

ADC1 CLK

OUT4

FPGA SYSREF

OUT5

FPGA DEV CLK

OUT6

FPGA MGMT CLK

OUT7

DAC0 SYSREF

OUT8

DAC0 CLK

OUT9

DAC1 SYSREF

OUT10

DAC1 CLK

Determining Output Divider Values

Since the desired frequencies of each output are already

determined, the output divider values can be calculated

using Equation 4. The results are shown in Table 13.

Table 13. Output Divide Settings for EZSync Standalone Design

Example

OUTPUT

PURPOSE

FREQUENCY

(MHz)

DIVIDE VALUE

(Mx)

OUT0

ADC0 SYSREF

12.5

320

OUT1

ADC0 CLK

500

OUT2

ADC1 SYSREF

12.5

320

OUT3

ADC1 CLK

500

OUT4

FPGA SYSREF

12.5

320

OUT5

FPGA DEV CLK

125

OUT6

FPGA MGMT CLK

100

OUT7

DAC0 SYSREF

12.5

320

OUT8

DAC0 CLK

4000

OUT9

DAC1 SYSREF

12.5

320

OUT10

DAC1 CLK

4000

Determining Output Digital Delay Values

The output digital delay is used to control phase relation-

ships between outputs. The minimum delay step is ½

of a period of the incoming input signal. For this design

example, the digital delay is used to place each device’s

SYSREF signal edges into a known phase relationship

to its corresponding device clock, optimized for the set-

up (ts) and hold time (th) requirements for that device.

Assume that the optimum SYSREF edge location for each

device occurs on the first falling clock edge before the

desired SYSREF valid rising clock edge. In other words,

SYSREF should change states ½ of a corresponding

device clock period before the SYSREF valid device clock

edge. Refer to Figure 23 for an example.

Figure 23. SYSREF Edge Timing Example

DEVICE CLOCK

SYSREF

6953F23

SYSREF

TRANSITION

TARGET RANGE

DESIRED SYSREF

VALID CLOCK EDGE

LTC6953 数据表(PDF) 33 Page - Analog Devices

LTC6953 数据表(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载

链接网址

LTC6953 数据表(PDF) 33 Page - Analog Devices

LTC6953 数据表(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表 下载

链接网址

数据表下载