LTC6953 datasheet(23/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

leave the SRQMD bit set to “0” until a SYSREF request is

required. When a SYSREF signal is needed, set SRQMD

to “1”, return the PDx bits to “0”, then wait at least 50µs

before issuing a SYSREF request. Put the SYSREF outputs

back into low power mode (PDx = 2) and set SRQMD = 0

when finished.

SERIAL PORT

The SPI-compatible serial port provides control and moni-

toring functionality. A configurable status output STAT

gives additional instant monitoring.

Communication Sequence

The serial bus is composed of CS, SCLK, SDI, and SDO.

Data transfers to the part are accomplished by the serial

bus master device first taking CS low to enable the

LTC6953’s port. Input data applied on SDI is clocked on

the rising edge of SCLK, with all transfers MSB first. The

OPERATION

communication burst is terminated by the serial bus mas-

ter returning CS high. See Figure 11 for details.

Data is read from the part during a communication burst

using SDO. Readback may be multidrop (more than one

LTC6953 connected in parallel on the serial bus), as SDO

is three-stated (Hi-Z) when CS is high or when data is

not being read from the part. If the LTC6953 is not used

in a multidrop configuration or if the serial port master

is not capable of setting the SDO line level between read

sequences, it is recommended to attach a high value

resistor of greater than 200k between SDO and GND to

ensure the line returns to a known level during Hi-Z states.

See Figure 12 for details.

Single Byte Transfers

The serial port is arranged as a simple memory map,

with status and control available in 56, byte-wide regis-

ters. All data bursts are comprised of at least two bytes.

MASTER–CS

MASTER–SCLK

tCSS

tCS

tCH

DATA

6953 F11

tCKL

tCKH

tCSS

tCSH

MASTER–SDI

MASTER–CS

MASTER–SCLK

LTC6953–SDO

Hi-Z

6953 F12

8TH CLOCK

DATA

tDO

Figure 11. Serial Port Write Timing Diagram

Figure 12. Serial Port Read Timing Diagram

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