LTC6953 datasheet(52/56 Pages) AD

52 / 56 page

LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

TYPICAL APPLICATIONS

ParallelSync Multichip Synchronization with Request Pass-Through

5ns/DIV

CARD #1

CARD #2

CARD #3

CARD #4

CARD #5

6953 TAO3b

STAGE 1 ADEL ADJUSTMENTS

REF EDGE ALIGNED < ±5.5ps

(ADJUSTS FOR PART, CABLE

AND PCB MISMATCH)

SYSREF VALID

CLOCK EDGE

500ps/DIV

OUT0: SYSREF

12.5MHz

OUT1: CLOCK

500MHz

OUT7: SYSREF

12.5MHz

OUT8: CLOCK

4GHz

6953 TA03d

100ns/DIV

SYSREF

300mV/DIV

6953 TAO3e

Step 1: Reference Alignment at

Daughter Card Inputs

Step 2: ParallelSync Multichip

Clock Alignment

Step 3: SYSREF Alignment

Step 3: SYSREF Pulses

Stage 2 LTC6952 Phase Noise vs

Stage 1 LTC6953 ADEL Setting

fOUT = 4GHz, Mx = 1

1µF

61.9Ω

1µF

100Ω

33nF

22nF

48.7Ω

1.2µF

48.7Ω

0.1µF

75Ω

30Ω

0.1µF

0.47µF

1µF

100Ω

1µF

OUT0+

OUT0 –

OUT1+

OUT1

–

OUT2+

OUT2–

OUT10+

OUT10–

OUT3+

OUT3–

OUT4+

OUT4–

OUT5+

OUT5–

OUT6+

OUT6–

OUT7+

OUT7–

OUT8+

OUT8–

OUT9+

OUT9–

LTC6953

IN+

IN–

EZS_SRQ+

EZS_SRQ–

CRYSTEK

CCHD-575-25-100

100MHz REF OSC

DAUGHTER

CARD #2

DAUGHTER

CARD #3

DAUGHTER

CARD #4

DAUGHTER

CARD #5

STAGE 1

STAGE 2

CRYSTEK

CVCO55CC-

4000-4000

VCO+

VCO–

VTUNE

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

OUT10+

OUT10–

OUT3+

OUT3–

OUT4+

OUT4–

OUT5+

OUT5–

OUT6+

OUT6–

OUT7+

OUT7–

OUT8+

OUT8–

OUT9+

OUT9–

LTC6952

12.5MHz SYSREF

500MHz CLOCK

4GHz CLOCK

125MHz CLOCK

100MHz CLOCK

DAUGHTER CARD #1

DAUGHTER CARD #2

DAUGHTER CARD #3

DAUGHTER CARD #4

DAUGHTER CARD #5

100MHz REF CLK

SSRQ PASS THRU

REF +

REF –

EZS_SRQ+

EZS_SRQ–

INITIAL SETUP: PROGRAM LTC6952 AND LTC6953 REGISTERS SETTINGS CREATED FROM THE LTC6952Wizard.

STEP 1: SYNCHRONIZE STAGE 1 REFERENCE SIGNALS

A) EZSync: TOGGLE STAGE 1 LTC6953 SSRQ BIT

B) OPT: FINE ALIGNMENT, ADJUST STAGE 1 ADEL BITS

STEP 2: SYNCHRONIZE STAGE 2 OUTPUT SIGNALS

A) SET STAGE 1 LTC6953 SRQMD = 1

B) ParallelSync, TOGGLE STAGE 1 LTC6953 SSRQ BIT

STEP 3: SEND SYSREF REQUEST

A) POWER UP LTC6952 SYSREF OUTPUTS

B) SET LTC6952 SRQMD = 1

C) SEND SYSREF, TOGGLE STAGE 1 LTC6953 SSRQ BIT

STEP 4: OPTIONAL REDUCE POWER

A) POWER DOWN LTC6952 SYSREF OUTPUTS

B) SET STAGE 1 LTC6953 AND LTC6952 SRQMD = 0

6953 TAO3a

RMS JITTER = 73fs

EQUIVALENT ADC

SNR METHOD

STAGE 1 ADEL = 0

STAGE 1 ADEL = 31

STAGE 1 ADEL = 63

OFFSET FREQUENCY (Hz)

10k

100k

10M 40M

–180

–170

–160

–150

–140

–130

–120

–110

–100

6953 TAO3f

500ps/DIV

OUT8: 4GHz

CARD #1

OUT1: 500MHz

CARD #1

OUT8: 4GHz

CARDS #2–5

OUT1: 500MHz

CARDS #2–5

6953 TAO3c

LTC6953 数据表(PDF) 52 Page - Analog Devices

LTC6953 数据表(HTML) 52 Page - Analog Devices

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LTC6953 数据表(PDF) 52 Page - Analog Devices

LTC6953 数据表(HTML) 52 Page - Analog Devices

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