LTC6953 datasheet(16/56 Pages) AD

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LTC6953

Rev 0

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

matched-length traces. OINVx also determines the state

of the output in a muted condition (PDx = 1) as shown in

Table 3. See Figure 3 for circuit details.

Figure 3. Simplified CML Interface Schematic (All OUTx)

VOUT

OUTx –

OUTx +

33Ω

50Ω

6953 F03

OUTPUT SYNCHRONIZATION AND SYSREF

GENERATION

The LTC6953 has circuitry to allow all outputs to be syn-

chronized into known phase alignments in multiple ways

to suit different applications using the EZSync Multichip

Clock Edge Synchronization protocol. Synchronization

can be between any combination of outputs on the same

chip (EZSync Standalone) or across multiple cascaded

FOLLOWER chips (EZSync Multichip). Once the out-

puts are at the correct frequency and synchronized, the

LTC6953 also has the ability to produce free running,

gated or finitely pulsed SYSREF signals as indicated by

the JESD204B subclass 1 specification.

EZS_SRQ Input Buffer

Both synchronization and SYSREF requests are achieved

by either a software signal (bit SSRQ in register h0B) or

a voltage signal on the EZS_SRQ± pins. The voltage on

these pins may be any differential signal within the speci-

fications in the Electrical Characteristics or alternatively

a CMOS signal on EZS_SRQ+ while EZS_SRQ– is tied to

GND. A simplified schematic of the EZS_SRQ input is

shown in Figure 4. When using the SSRQ bit, the state of

the EZS_SRQ± pins must be a logic “0”, easily achieved

by setting both EZS_SRQ± pins to GND. Likewise, when

using the EZS_SRQ± pins, bit SSRQ must be set to “0”.

Bit SRQMD determines the type of request issued by

the EZS_SRQ± pins or SSRQ bit. When SRQMD = 0,

the request is for synchronization of the outputs. When

SRQMD = 1, it is a request to output SYSREF pulses.

Note that synchronization MUST be performed before a

SYSREF request. The synchronization must be repeated

only if the divider setting is changed or if the divider is

powered down.

Synchronization Overview

The goal of synchronization is to align all output divid-

ers on single or multiple LTC6953s (or other compat-

ible Analog Devices clocking parts) into a known phase

relationship. At initial power-up, after a power-on reset

(POR) or any time the output divide values are changed,

the outputs will not be synchronized. Any changes to the

output digital delays (DDELx) will not be reflected until

after synchronization. Although the outputs will be at the

correct frequency without synchronization, the phases

will have an unknown relationship until a synchronization

event occurs.

To enable synchronization on the LTC6953, the SRQMD

bit in register h0B must be set to “0”. Synchronization

begins either with the EZS_SRQ input driven to a high

state or by writing “1” to the SSRQ bit. For any output with

its SRQENx bit set to “1”, the output divider will stop run-

ning and return to a logic “0” state after an internal timing

delay of greater than 100µs. The EZS_SRQ input state or

SSRQ bit must remain high for a minimum of 1ms.

Figure 4. Simplified EZS_SRQ Interface Schematic

VREF

BIAS

28k

EZS_SRQ+

EZS_SRQ–

0.8V

CMOS

2.1V

6953 F04

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