LTC6953 datasheet(42/56 Pages) AD

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LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Table 20. FOLLOWER Output Register Settings for EZSync

Multichip Design Example

ADDR

VALUE

ADDR

VALUE

ADDR

VALUE

h0C

h00

h1C

h00

h2C

h00

h0D

h00

h1D

h80

h2D

h80

h0E

h00

h1E

h20

h2E

h20

h0F

h00

h1F

h00

h2F

h00

h10

h9C

h20

h9C

h30

h9C

h11

hE0

h21

hE0

h31

hE0

h12

h00

h22

h1F

h32

h1F

h13

h00

h23

h00

h33

h00

h14

hF8

h24

h00

h34

h00

h15

h80

h25

h80

h35

h80

h16

h20

h26

h20

h36

h20

h17

h00

h27

h00

h37

h00

h18

h9C

h28

h9C

h19

hE0

h29

hE0

h1A

h1F

h2A

h1F

h1B

h00

h2B

h00

Synchronization

The outputs in this example are now running at the desired

frequency, but have random phase relationships with

each other. Synchronization forces the outputs to run at

known and repeatable phases and can be achieved in this

example either externally, by driving the CONTROLLER’s

EZS_SRQ± pins or internally, with the CONTROLLER’s

SSRQ bit in Reg0B. Since the part was just programmed,

set the SSRQ bit to “1” and hold the EZS_SRQ± pins low:

CONTROLLER Reg0B = h05

After waiting a minimum of 1ms, set SSRQ back to “0”:

CONTROLLER Reg0B = h04

Once the internal synchronization process completes, the

outputs will be aligned as shown in Figure 27. Note that the

internal divider behavior for the muted SYSREF outputs is

shown as well as the actual outputs to demonstrate the

phase alignment following synchronization. Also notice

that all FOLLOWER outputs will have additional delay from

the CONTROLLER outputs equal to the FOLLOWER’s tPD

as described in the Electrical Characteristics.

Putting the ICs Into a Lower Power Mode

If desired, both ICs can be placed into lower power modes

while awaiting a SYSREF request. This is achieved by set-

ting PDx = 2 for all SYSREF-defined outputs. This powers

down the output driver circuitry but leaves the internal

divider running and in the correct phase relationship to

the clocks.

Performing a SYSREF Request

To produce SYSREF pulses, write a “1” to SRQMD and

take the parts out of low power mode (if used) by writing

all the SYSREF output PDx bits to “0”. Wait 50µs to allow

circuitry to power up. Send the SYSREF request by writing

a “1” to the CONTROLLER SSRQ bit in Reg0B:

CONTROLLER Reg0B = h05

After waiting a minimum of 1ms, write Reg0B again:

CONTROLLER Reg0B = h04

Place the ICs back into low power mode if desired by writ-

ing a “0” to SRQMD and setting PDx = 2 for all SYSREF-

defined outputs. After the rising edge of the SYSREF

request, the SYSREF outputs will pulse four times and

then return to a “0” state as shown in Figure 28. Note

that the FOLLOWER SYSREF pulses may not start and

stop at exactly the same time as the CONTROLLER’s.

This is not an issue, since the SYSREF edges will still be

aligned correctly.

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