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DRA821U4...ALM 数据表(PDF) 32 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 32 Page - Texas Instruments

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Table 6-1. Pin Attributes (continued)
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
TYPE
[5]
BALL
RESET
STATE
[6]
BALL
RESET
REL. MUX
MODE
[7]
I/O
VOLTAGE
VALUE
[8]
POWER
[9]
HYS
[10]
BUFFER
TYPE
[11]
PULL
UP/DOWN
TYPE
[12]
DSIS
[13]
RX
ACTIVE/
TX
DISABLE
[14]
IO
RET
[15]
K19
OSC1_XI
OSC1_XI
I
1.8 V
VDDA_OSC1
Yes
HFOSC
J19
OSC1_XO
OSC1_XO
O
1.8 V
VDDA_OSC1
Yes
HFOSC
C15
PMIC_POWER_EN1
PMIC_POWER_EN1
0
O
OFF
7
1.8 V/3.3 V
VDDSHV0_MCU
Yes
LVCMOS
PU/PD
Yes
MCU_I3C0_SDAPULLEN
5
OD
WKUP_GPIO0_68
7
IO
pad
T19
PMIC_WAKE0n
PMIC_WAKE0n
0
OD
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
RGMII4_TD1
4
O
GPIO0_1
7
IO
pad
H20
PORz
PORz
0
I
0
1.8 V
VDDA_WKUP,
VDDA_POR_WKUP
Yes
FS RESET
U2
RESETSTATz
RESETSTATz
0
O
PD
0
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
A15
RESET_REQz
RESET_REQz
0
I
OFF
0
1.8 V/3.3 V
VDDSHV0_MCU
Yes
LVCMOS
PU/PD
AA20
RMII1_CRS_DV
RMII1_CRS_DV
0
I
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
0
1/0
Yes
RGMII1_RD2
4
I
0
RMII1_CRS_DV
5
I
0
GPIO0_4
7
IO
pad
EHRPWM2_B
9
IO
0
TRC_DATA7
10
O
UART4_TXD
11
O
MCASP1_AXR1
12
IO
0
GPMC0_AD2
14
IO
0
Y17
RMII1_RX_ER
RMII1_RX_ER
0
I
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
0
1/0
Yes
RGMII1_RD3
4
I
0
RMII1_RX_ER
5
I
0
GPIO0_5
7
IO
pad
EHRPWM2_A
9
IO
0
TRC_DATA6
10
O
UART6_TXD
11
O
MCASP1_AXR0
12
IO
0
GPMC0_AD3
14
IO
0
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
32
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Product Folder Links: DRA821U-Q1



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