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DRA821U4...ALM 数据表(PDF) 72 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 72 Page - Texas Instruments |
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72 / 252 page  Table 6-85. GPMC0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPMC0_AD4 GPMC Data 4 Input/Output in A/D non-multiplexed mode and additionally Address 5 Output in A/D multiplexed mode IO Y16 GPMC0_AD5 GPMC Data 5 Input/Output in A/D non-multiplexed mode and additionally Address 6 Output in A/D multiplexed mode IO V17 GPMC0_AD6 GPMC Data 6 Input/Output in A/D non-multiplexed mode and additionally Address 7 Output in A/D multiplexed mode IO AA19 GPMC0_AD7 GPMC Data 7 Input/Output in A/D non-multiplexed mode and additionally Address 8 Output in A/D multiplexed mode IO V16 GPMC0_AD8 GPMC Data 8 Input/Output in A/D non-multiplexed mode and additionally Address 9 Output in A/D multiplexed mode IO Y18 GPMC0_AD9 GPMC Data 9 Input/Output in A/D non-multiplexed mode and additionally Address 10 Output in A/D multiplexed mode IO Y19 GPMC0_AD10 GPMC Data 10 Input/Output in A/D non-multiplexed mode and additionally Address 11 Output in A/D multiplexed mode IO Y21 GPMC0_AD11 GPMC Data 11 Input/Output in A/D non-multiplexed mode and additionally Address 12 Output in A/D multiplexed mode IO W15 GPMC0_AD12 GPMC Data 12 Input/Output in A/D non-multiplexed mode and additionally Address 13 Output in A/D multiplexed mode IO Y20 GPMC0_AD13 GPMC Data 13 Input/Output in A/D non-multiplexed mode and additionally Address 14 Output in A/D multiplexed mode IO U14 GPMC0_AD14 GPMC Data 14 Input/Output in A/D non-multiplexed mode and additionally Address 15 Output in A/D multiplexed mode IO U16 GPMC0_AD15 GPMC Data 15 Input/Output in A/D non-multiplexed mode and additionally Address 16 Output in A/D multiplexed mode IO U15 GPMC0_BE0n_CLE GPMC Lower-Byte Enable (active low) or Command Latch Enable O U20 GPMC0_BE1n GPMC Upper-Byte Enable (active low) O AA15 GPMC0_CSn0 GPMC Chip Select 0 (active low) O T20 GPMC0_CSn1 GPMC Chip Select 1 (active low) O U21 GPMC0_CSn2 GPMC Chip Select 2 (active low) O W17 GPMC0_CSn3 GPMC Chip Select 3 (active low) O AA16 GPMC0_WAIT0 GPMC External Indication of Wait I T16 GPMC0_WAIT1 GPMC External Indication of Wait I U17 6.3.20 MMC 6.3.20.1 MAIN Domain Table 6-86. MMC0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MMC0_CALPAD (1) MMC/SD/SDIO Calibration Resistor A P20 MMC0_CLK MMC/SD/SDIO Clock O P18 DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 72 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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