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DRA821U4...ALM 数据表(PDF) 24 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 24 Page - Texas Instruments

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Table 6-1. Pin Attributes (continued)
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
TYPE
[5]
BALL
RESET
STATE
[6]
BALL
RESET
REL. MUX
MODE
[7]
I/O
VOLTAGE
VALUE
[8]
POWER
[9]
HYS
[10]
BUFFER
TYPE
[11]
PULL
UP/DOWN
TYPE
[12]
DSIS
[13]
RX
ACTIVE/
TX
DISABLE
[14]
IO
RET
[15]
AA15
MCAN12_TX
MCAN12_TX
0
O
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1/0
Yes
RGMII2_RD1
4
I
0
MCAN12_TX
6
O
GPIO0_33
7
IO
pad
SPI2_CS2
8
IO
1
EQEP1_A
9
I
0
I2C6_SCL
10
IOD
1
UART2_RXD
11
I
1
MCASP0_AXR15
12
IO
0
GPMC0_BE1n
13
O
GPMC0_A17
14
OZ
AA16
MCAN13_RX
MCAN13_RX
0
I
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1
1/0
Yes
RGMII2_RX_CTL
4
I
0
GPMC0_CSn3
5
O
MCAN13_RX
6
I
1
GPIO0_36
7
IO
pad
SPI2_D1
8
IO
0
EQEP0_I
9
IO
0
I2C5_SDA
10
IOD
1
UART8_RTSn
11
O
MCASP2_AXR0
12
IO
0
I3C0_SDA
13
IO
1
GPMC0_A20
14
OZ
AA18
MCAN13_TX
MCAN13_TX
0
O
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1/0
Yes
RGMII2_RD3
4
I
0
GPMC0_WPn
5
O
MCAN13_TX
6
O
GPIO0_35
7
IO
pad
SPI2_D0
8
IO
0
EQEP0_S
9
IO
0
I2C5_SCL
10
IOD
1
UART8_CTSn
11
I
1
MCASP1_AXR9
12
IO
0
I3C0_SCL
13
IO
1
GPMC0_A19
14
OZ
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
24
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DRA821U-Q1



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