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DRA821U4...ALM 数据表(PDF) 21 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 21 Page - Texas Instruments

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Table 6-1. Pin Attributes (continued)
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
TYPE
[5]
BALL
RESET
STATE
[6]
BALL
RESET
REL. MUX
MODE
[7]
I/O
VOLTAGE
VALUE
[8]
POWER
[9]
HYS
[10]
BUFFER
TYPE
[11]
PULL
UP/DOWN
TYPE
[12]
DSIS
[13]
RX
ACTIVE/
TX
DISABLE
[14]
IO
RET
[15]
U19
MCAN8_RX
MCAN8_RX
0
I
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1
1/0
Yes
RGMII3_TD1
4
O
RMII3_TXD1
5
O
MCAN8_RX
6
I
1
GPIO0_26
7
IO
pad
SPI3_CS3
8
IO
1
EHRPWM3_SYNCO
9
O
TRC_DATA14
10
O
UART3_RTSn
11
O
MCASP0_AXR4
12
IO
0
GPMC0_A8
13
OZ
UART0_DSRn
14
I
1
T15
MCAN8_TX
MCAN8_TX
0
O
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1/0
Yes
GPMC0_A7
3
OZ
RGMII3_TD0
4
O
RMII3_TX_EN
5
O
MCAN8_TX
6
O
GPIO0_25
7
IO
pad
SPI3_CS2
8
IO
1
EHRPWM_TZn_IN3
9
I
0
TRC_DATA15
10
O
UART3_CTSn
11
I
1
MCASP0_AXR5
12
IO
0
UART0_DCDn
14
I
1
U18
MCAN9_RX
MCAN9_RX
0
I
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1
1/0
Yes
RGMII3_TD3
4
O
MCAN9_RX
6
I
1
GPIO0_28
7
IO
pad
SPI3_D0
8
IO
0
EHRPWM3_B
9
IO
0
TRC_DATA12
10
O
MCASP1_ACLKR
12
IO
0
GPMC0_A10
13
OZ
MCASP1_AXR11
14
IO
0
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DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: DRA821U-Q1



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