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DRA821U4...ALM 数据表(PDF) 51 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 51 Page - Texas Instruments

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Table 6-4. DDRSS Signal Mapping (continued)
SIGNAL NAME [1]
MEMORY TYPE
PIN TYPE [3]
BALL [4]
LPDDR4
DDR0_DQ10
DQ10
IO
F2
DDR0_DQ11
DQ11
IO
E3
DDR0_DQ12
DQ12
IO
F3
DDR0_DQ13
DQ13
IO
F4
DDR0_DQ14
DQ14
IO
D4
DDR0_DQ15
DQ15
IO
F5
DDR0_DQ16
DQ16
IO
K4
DDR0_DQ17
DQ17
IO
L4
DDR0_DQ18
DQ18
IO
M4
DDR0_DQ19
DQ19
IO
L3
DDR0_DQ20
DQ20
IO
L2
DDR0_DQ21
DQ21
IO
L1
DDR0_DQ22
DQ22
IO
M3
DDR0_DQ23
DQ23
IO
N2
DDR0_DQ24
DQ24
IO
R3
DDR0_DQ25
DQ25
IO
T1
DDR0_DQ26
DQ26
IO
P1
DDR0_DQ27
DQ27
IO
P2
DDR0_DQ28
DQ28
IO
N4
DDR0_DQ29
DQ29
IO
P3
DDR0_DQ30
DQ30
IO
P4
DDR0_DQ31
DQ31
IO
N5
DDR0_DM0
DMI0
IO
A3
DDR0_DM1
DMI1
IO
E4
DDR0_DM2
DMI2
IO
N1
DDR0_DM3
DMI3
IO
R4
DDR0_DQS0N
DQS0
IO
B1
DDR0_DQS0P
DQS0_n
IO
B2
DDR0_DQS1N
DQS1
IO
E1
DDR0_DQS1P
DQS1_n
IO
E2
DDR0_DQS2N
DQS2
IO
M1
DDR0_DQS2P
DQS2_n
IO
M2
DDR0_DQS3N
DQS3
IO
R1
DDR0_DQS3P
DQS3_n
IO
R2
DDR0_RESETn
RESET_n
IO
J5
DDR0_CAL0
VTP
A
K5
DDR0_CKE0
IO
G2
DDR0_CKE1
IO
H2
DDR0_CSn0_0
IO
G3
DDR0_CSn0_1
IO
K2
DDR0_CSn1_0
IO
G5
DDR0_CSn1_1
IO
J3
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DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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