DRA821U4...ALM datasheet(7/252 Pages) TI

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• (MMCSD1 Switching Characteristics – UHS-I SDR25 Mode): Updated the MAX value for SDR258 and

SDR259.......................................................................................................................................................... 206

• (MMCSD1 Switching Characteristics – UHS-I DDR50 Mode): Updated/Changed the MAX value for both

DDR508 and DDR509 delay times................................................................................................................. 207

• (MMCSD1 Switching Characteristics – UHS-I SDR104 Mode): Updated the MIN value for SDR1046 and

SDR1047........................................................................................................................................................ 209

• (MMCSD1 Switching Characteristics – UHS-I SDR104 Mode): Updated the MIN and MAX values for

SDR1048 and SDR1049.................................................................................................................................209

• (OSPI): Updated/Changed timing specification values for OSPI.................................................................... 210

• Updated O4 and O5 values in OSPI Switching Characteristics – DDR Mode table....................................... 211

• Updated O10 and O11 values in OSPI Switching Characteristics – SDR Mode table................................... 212

• Updated min values in OSPI Timing Requirements – SDR Mode table......................................................... 214

• (OSPI DLL Delay Mapping for Timing Modes ): Updated/Chnged 1.8 V, 3.3 V, and Other table rows for

MODE: TRANSMIT and RECEIVE.................................................................................................................214

• (UART Timing Conditions): Added a note to the maximum output load capacitance value........................... 216

• (UART Timing Requirements): Changed the start pulse width parameter description and added a note that

clarifies the data valid time requirements for each parameter in the table..................................................... 216

• (UART Switching Characteristics): Updated the "Maximum Programmable Baud Rate"; deleted MODE

column and 30-pF row.................................................................................................................................... 216

• (UART Switching Characteristics): Changed the start pulse width parameter description, removed the CTS

delay parameter, and removed the load capacitance references from the Programmable baud rate parameter

........................................................................................................................................................................216

• (UART Timing): Updated the timing diagram image to remove CTS and show RXD timing relative to VIL and

VIH ..................................................................................................................................................................216

• Added PCB Connectivity Requirements to the Debug Trace Timing Conditions table...................................217

• Added a note that describes the how the JTAG port is split across two IO power domains and the effect on

timing.............................................................................................................................................................. 218

• Changed the minimum input slew rate value in the Debug Trace Timing Conditions table from 0.25 V/ns to

0.50 V/ns.........................................................................................................................................................218

• Added PCB Connectivity Requirements to the Debug Trace Timing Conditions table...................................218

• Changed the minimum pulse width value to a function of TCK and added notes to minimum cycle time and

pulse width parameters...................................................................................................................................219

• (Detailed Description/DDRSS): Added a sentence to the "The DDR subsystem in this device comprises .."

paragraph along with a Note...........................................................................................................................223

• (Standard Package Symbolization): Updated/Changed the lead-in paragraph.............................................. 240

• (Device Naming Convention): Added additional Device Types and associated footnotes to the Nomenclature

Description table............................................................................................................................................. 241

• (Tools and Software): Deleted the "Clock Tree Tool (CTT)", the "Power Estimation Tool (PET)" , and the Pin

Mux Tool......................................................................................................................................................... 243

• (Tools and Software): Added the SYSCONFIG tool....................................................................................... 243

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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