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DRA821U4...ALM 数据表(PDF) 18 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 18 Page - Texas Instruments

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Table 6-1. Pin Attributes (continued)
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
TYPE
[5]
BALL
RESET
STATE
[6]
BALL
RESET
REL. MUX
MODE
[7]
I/O
VOLTAGE
VALUE
[8]
POWER
[9]
HYS
[10]
BUFFER
TYPE
[11]
PULL
UP/DOWN
TYPE
[12]
DSIS
[13]
RX
ACTIVE/
TX
DISABLE
[14]
IO
RET
[15]
Y21
MCAN3_TX
MCAN3_TX
0
O
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1/0
Yes
RGMII1_TD2
4
O
RMII4_CRS_DV
5
I
0
MCAN3_TX
6
O
GPIO0_15
7
IO
pad
SPI5_D0
8
IO
0
EHRPWM0_A
9
IO
0
TRC_DATA1
10
O
MCASP0_AXR1
12
IO
0
GPMC0_AD10
14
IO
0
Y20
MCAN4_RX
MCAN4_RX
0
I
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1
1/0
Yes
RGMII1_TXC
4
O
RMII4_TX_EN
5
O
MCAN4_RX
6
I
1
GPIO0_18
7
IO
pad
SPI5_D1
8
IO
0
EHRPWM1_B
9
IO
0
TRC_DATA4
10
O
I2C2_SDA
11
IOD
1
MCASP0_AXR2
12
IO
0
GPMC0_AD12
14
IO
0
W15
MCAN4_TX
MCAN4_TX
0
O
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1/0
Yes
RGMII1_TX_CTL
4
O
RMII4_TXD0
5
O
MCAN4_TX
6
O
GPIO0_17
7
IO
pad
SPI5_CLK
8
IO
0
EHRPWM0_SYNCI
9
I
0
TRC_CLK
10
O
I2C2_SCL
11
IOD
1
MCASP0_ACLKX
12
IO
0
GPMC0_AD11
14
IO
0
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
18
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DRA821U-Q1



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