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DRA821U4...ALM 数据表(PDF) 33 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 33 Page - Texas Instruments

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Table 6-1. Pin Attributes (continued)
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
TYPE
[5]
BALL
RESET
STATE
[6]
BALL
RESET
REL. MUX
MODE
[7]
I/O
VOLTAGE
VALUE
[8]
POWER
[9]
HYS
[10]
BUFFER
TYPE
[11]
PULL
UP/DOWN
TYPE
[12]
DSIS
[13]
RX
ACTIVE/
TX
DISABLE
[14]
IO
RET
[15]
V17
RMII1_TX_EN
RMII1_TX_EN
0
O
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1/0
Yes
RGMII4_RXC
4
I
0
RMII1_TX_EN
5
O
GPIO0_7
7
IO
pad
EQEP2_A
9
I
0
UART9_TXD
11
O
MCASP0_AXR8
12
IO
0
I2C1_SCL
13
IOD
1
GPMC0_AD5
14
IO
0
AA17
RMII1_RXD0
RMII1_RXD0
0
I
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
0
1/0
Yes
RGMII1_RD0
4
I
0
RMII1_RXD0
5
I
0
MCAN14_TX
6
O
GPIO0_2
7
IO
pad
TRC_DATA9
10
O
UART5_TXD
11
O
MCASP1_AXR3
12
IO
0
GPMC0_AD0
14
IO
0
Y15
RMII1_RXD1
RMII1_RXD1
0
I
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
0
1/0
Yes
RGMII1_RD1
4
I
0
RMII1_RXD1
5
I
0
MCAN14_RX
6
I
1
GPIO0_3
7
IO
pad
EHRPWM_TZn_IN2
9
I
0
TRC_DATA8
10
O
UART5_RXD
11
I
1
MCASP1_AXR2
12
IO
0
GPMC0_AD1
14
IO
0
Y16
RMII1_TXD0
RMII1_TXD0
0
O
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1/0
Yes
RGMII1_RX_CTL
4
I
0
RMII1_TXD0
5
O
GPIO0_6
7
IO
pad
EHRPWM0_SYNCO
9
O
TRC_CTL
10
O
UART6_RXD
11
I
1
MCASP0_AFSX
12
IO
0
GPMC0_AD4
14
IO
0
www.ti.com
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: DRA821U-Q1



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