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DRA821U4...ALM 数据表(PDF) 39 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 39 Page - Texas Instruments

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Table 6-1. Pin Attributes (continued)
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
TYPE
[5]
BALL
RESET
STATE
[6]
BALL
RESET
REL. MUX
MODE
[7]
I/O
VOLTAGE
VALUE
[8]
POWER
[9]
HYS
[10]
BUFFER
TYPE
[11]
PULL
UP/DOWN
TYPE
[12]
DSIS
[13]
RX
ACTIVE/
TX
DISABLE
[14]
IO
RET
[15]
T17
UART0_TXD
UART0_TXD
0
O
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Yes
RGMII4_TD2
4
O
GPIO0_48
7
IO
pad
GPMC0_WEn
14
O
T18
UART1_RXD
UART1_RXD
0
I
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1
Yes
MCAN17_TX
1
O
TIMER_IO6
3
IO
0
RGMII4_TD3
4
O
GPIO0_49
7
IO
pad
GPMC0_OEn_REn
14
O
T20
UART1_TXD
UART1_TXD
0
O
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Yes
MCAN17_RX
1
I
1
TIMER_IO7
3
IO
0
RGMII4_TX_CTL
4
O
GPIO0_50
7
IO
pad
GPMC0_CSn0
14
O
V14
UART2_RXD
UART2_RXD
0
I
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1
0/0
Yes
RGMII2_TD2
4
O
RMII2_CRS_DV
5
I
0
GPIO0_39
7
IO
pad
SPI6_CLK
8
IO
0
GPMC0_CLKOUT
9
O
GPMC0_FCLK_MUX
10
O
UART2_RXD
11
I
1
MCASP2_AXR3
12
IO
0
OBSCLK2
14
O
V13
UART2_TXD
UART2_TXD
0
O
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Yes
RGMII2_TD3
4
O
RMII2_RX_ER
5
I
0
GPIO0_40
7
IO
pad
SPI6_D0
8
IO
0
UART2_TXD
11
O
MCASP2_AFSX
12
IO
0
www.ti.com
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: DRA821U-Q1



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