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DRA821U4...ALM 数据表(PDF) 15 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 15 Page - Texas Instruments

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Table 6-1. Pin Attributes (continued)
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
TYPE
[5]
BALL
RESET
STATE
[6]
BALL
RESET
REL. MUX
MODE
[7]
I/O
VOLTAGE
VALUE
[8]
POWER
[9]
HYS
[10]
BUFFER
TYPE
[11]
PULL
UP/DOWN
TYPE
[12]
DSIS
[13]
RX
ACTIVE/
TX
DISABLE
[14]
IO
RET
[15]
U3
ECAP0_IN_APWM_OUT
ECAP0_IN_APWM_OUT
0
IO
OFF
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
0
SYNC0_OUT
1
O
CPTS0_RFT_CLK
2
I
I
I2C1_SCL
3
IOD
1
CPTS0_HW1TSPUSH
4
I
0
UART3_RXD
5
I
1
SPI7_CS0
6
IO
1
GPIO0_58
7
IO
pad
A13
EMU0
EMU0
0
IO
OFF
0
1.8 V/3.3 V
VDDSHV0_MCU
Yes
LVCMOS
PU/PD
0/0
D12
EMU1
EMU1
0
IO
OFF
0
1.8 V/3.3 V
VDDSHV0_MCU
Yes
LVCMOS
PU/PD
0/0
U6
EXTINTn
EXTINTn
0
I
OFF
7
1.8 V/3.3 V
VDDSHV0
Yes
I2C OD FS
1
GPIO0_0
7
IO
pad
T3
EXT_REFCLK1
EXT_REFCLK1
0
I
OFF
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
0
SYNC1_OUT
1
O
I2C1_SDA
3
IOD
1
CPTS0_HW2TSPUSH
4
I
0
UART3_TXD
5
O
SPI7_CLK
6
IO
0
GPIO0_59
7
IO
pad
U12
GPIO0_41
RGMII2_TX_CTL
4
O
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Yes
RMII2_TXD0
5
O
GPIO0_41
7
IO
pad
SPI6_D1
8
IO
0
UART4_RXD
11
I
1
MCASP2_ACLKX
12
IO
0
GPMC0_A13
13
OZ
U13
GPMC0_CLK
GPMC0_CLK
0
IO
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
0
Yes
USB0_DRVVBUS
1
O
RGMII4_RD3
4
I
0
GPIO0_44
7
IO
pad
SPI0_CS3
10
IO
1
UART9_RXD
11
I
1
V3
I2C0_SCL
I2C0_SCL
0
IOD
OFF
7
1.8 V/3.3 V
VDDSHV0
Yes
I2C OD FS
1
GPIO0_56
7
IO
pad
W2
I2C0_SDA
I2C0_SDA
0
IOD
OFF
7
1.8 V/3.3 V
VDDSHV0
Yes
I2C OD FS
1
GPIO0_57
7
IO
pad
www.ti.com
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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