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DRA821U4...ALM 数据表(PDF) 1 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 1 Page - Texas Instruments |
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1 / 252 page  DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep operation, 8K DMIPS – 32K I-Cache, 32K D-Cache, 64K L2 TCM – 2× Arm® Cortex®-R5F MCUs in isolated MCU subsystem – 2× Arm® Cortex®-R5F MCUs in general compute partition Memory subsystem: • 1MB of On-Chip L3 RAM with ECC and coherency – ECC error protection – Shared coherent cache – Supports internal DMA engine • External Memory Interface (EMIF) module with ECC – Supports LPDDR4 memory types that comply with the JESD209-4B specification. (No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits) – Supports speeds up to 3200 MT/s – 32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/s • General-Purpose Memory Controller (GPMC) • 512KB on-chip SRAM in MAIN domain, protected by ECC Virtualization: • Hypervisor support in Arm® Cortex®-A72 • Independent processing subsystems with Arm® Cortex®-A72, Arm® Cortex®-R5F with isolated safety MCU island • IO virtualization support – Peripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral traffic • Multi-region firewall support for memory and peripheral isolation • Virtualization support with Ethernet, PCIe, and DMA • Device security (on select part numbers): • Secure boot with secure runtime support • Customer programmable root key, up to RSA-4K or ECC-512 • Embedded hardware security module • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES Functional Safety: • Functional Safety-Compliant targeted (on select part numbers) – Developed for functional safety applications – Documentation will be available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted – Systematic capability up to ASIL-D/SIL-3 targeted – Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain – Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain – Hardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main Domain – FFI isolation provided between EMCU and the remainder of the Main Domain – Safety-related certification • ISO 26262 and IEC 61508 planned • AEC-Q100 qualified on part number variants ending in Q1 • High-speed interfaces: – Integrated Ethernet TSN/AVB switch supporting up to 4 (DRA821U4) or 2 (DRA821U2) external ports: • One port supports 5Gb, 10Gb USXGMII/XFI • All ports support 2.5Gb SGMII • All ports support 1Gb SGMII/RGMII • DRA821U4: Any single port can support QSGMII (using all 4 internal ports) • Non-blocking wire-rate store and forward switch • InterVLAN (Layer3) routing support • Time synchronization support with IEEE 1588(annex D,E,F) • TSN/AVB support for traffic scheduling, shaping • Port mirroring feature for debug and diagnostics • Policing and rate limiting support – One RGMII/RMII port in safety MCU island • One PCI-Express® Gen3 controller – Gen1, Gen2, and Gen3 operation with auto- negotiation – 4× lanes • One USB 3.1 Gen1 dual-role device subsystem – Supports type-C switching DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. |
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