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DRA821U4...ALM 数据表(PDF) 50 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 50 Page - Texas Instruments

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Table 6-3. DDRSS0 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN TYPE
[3]
BALL [4]
DDR0_DQ21
DDRSS Data
IO
L1
DDR0_DQ22
DDRSS Data
IO
M3
DDR0_DQ23
DDRSS Data
IO
N2
DDR0_DQ24
DDRSS Data
IO
R3
DDR0_DQ25
DDRSS Data
IO
T1
DDR0_DQ26
DDRSS Data
IO
P1
DDR0_DQ27
DDRSS Data
IO
P2
DDR0_DQ28
DDRSS Data
IO
N4
DDR0_DQ29
DDRSS Data
IO
P3
DDR0_DQ30
DDRSS Data
IO
P4
DDR0_DQ31
DDRSS Data
IO
N5
DDR0_DQS0N
DDRSS Complimentary Data Strobe
IO
B1
DDR0_DQS0P
DDRSS Data Strobe
IO
B2
DDR0_DQS1N
DDRSS Complimentary Data Strobe
IO
E1
DDR0_DQS1P
DDRSS Data Strobe
IO
E2
DDR0_DQS2N
DDRSS Complimentary Data Strobe
IO
M1
DDR0_DQS2P
DDRSS Data Strobe
IO
M2
DDR0_DQS3N
DDRSS Complimentary Data Strobe
IO
R1
DDR0_DQS3P
DDRSS Data Strobe
IO
R2
(1)
An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
6.3.2.2 DDRSS Mapping
Table 6-4 presents DDRSS interface signal mapping.
Table 6-4. DDRSS Signal Mapping
SIGNAL NAME [1]
MEMORY TYPE
PIN TYPE [3]
BALL [4]
LPDDR4
DDR0_CA0
CA0_A
IO
G4
DDR0_CA1
CA1_A
IO
H3
DDR0_CA2
CA2_A
IO
J4
DDR0_CA3
CA3_A
IO
K1
DDR0_CA4
CA4_A
IO
J2
DDR0_CA5
CA5_A
IO
H5
DDR0_CKP
CK_t_A
IO
H1
DDR0_CKN
CK_c_A
IO
G1
DDR0_DQ0
DQ0
IO
B4
DDR0_DQ1
DQ1
IO
A4
DDR0_DQ2
DQ2
IO
C4
DDR0_DQ3
DQ3
IO
C1
DDR0_DQ4
DQ4
IO
C3
DDR0_DQ5
DQ5
IO
C2
DDR0_DQ6
DQ6
IO
A2
DDR0_DQ7
DQ7
IO
B3
DDR0_DQ8
DQ8
IO
D1
DDR0_DQ9
DQ9
IO
D2
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
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