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DRA821U4...ALM 数据表(PDF) 38 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 38 Page - Texas Instruments

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Table 6-1. Pin Attributes (continued)
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
TYPE
[5]
BALL
RESET
STATE
[6]
BALL
RESET
REL. MUX
MODE
[7]
I/O
VOLTAGE
VALUE
[8]
POWER
[9]
HYS
[10]
BUFFER
TYPE
[11]
PULL
UP/DOWN
TYPE
[12]
DSIS
[13]
RX
ACTIVE/
TX
DISABLE
[14]
IO
RET
[15]
U5
SPI0_CS1
SPI0_CS1
0
IO
OFF
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
1
CPTS0_TS_COMP
1
O
UART0_RTSn
2
O
O
GPIO0_52
7
IO
pad
V4
SPI0_D0
SPI0_D0
0
IO
OFF
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
0
UART1_RTSn
1
O
I2C2_SDA
2
IOD
IOD
GPIO0_54
7
IO
pad
T5
SPI0_D1
SPI0_D1
0
IO
OFF
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
0
GPIO0_55
7
IO
pad
B15
TCK
TCK
0
I
0
1.8 V/3.3 V
VDDSHV0_MCU
Yes
LVCMOS
PU/PD
F19
TDI
TDI
0
I
OFF
0
1.8 V/3.3 V
VDDSHV0_MCU
Yes
LVCMOS
PU/PD
F21
TDO
TDO
0
OZ
OFF
0
1.8 V/3.3 V
VDDSHV0_MCU
Yes
LVCMOS
PU/PD
V1
TIMER_IO0
TIMER_IO0
0
IO
OFF
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
0
ECAP1_IN_APWM_OUT
1
IO
0
SYSCLKOUT0
2
O
O
UART3_CTSn
5
I
1
SPI7_D0
6
IO
0
GPIO0_60
7
IO
pad
MMC1_SDCD
8
I
1
W1
TIMER_IO1
TIMER_IO1
0
IO
OFF
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
0
0/0
ECAP2_IN_APWM_OUT
1
IO
0
OBSCLK0
2
O
O
UART3_RTSn
5
O
SPI7_D1
6
IO
0
GPIO0_61
7
IO
pad
MMC1_SDWP
8
I
1
PCIE1_CLKREQn
9
IO
0
U4
TMS
TMS
0
I
OFF
0
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
B20
TRSTn
TRSTn
0
I
0
1.8 V/3.3 V
VDDSHV0_MCU
Yes
LVCMOS
PU/PD
T16
UART0_RXD
UART0_RXD
0
I
OFF
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
1
0/0
Yes
RGMII4_TXC
4
O
GPIO0_47
7
IO
pad
GPMC0_WAIT0
14
I
0
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
38
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DRA821U-Q1



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