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DRA821U4...ALM 数据表(PDF) 37 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 37 Page - Texas Instruments

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Table 6-1. Pin Attributes (continued)
BALL
NUMBER
[1]
BALL
NAME
[2]
SIGNAL
NAME
[3]
MUX
MODE
[4]
TYPE
[5]
BALL
RESET
STATE
[6]
BALL
RESET
REL. MUX
MODE
[7]
I/O
VOLTAGE
VALUE
[8]
POWER
[9]
HYS
[10]
BUFFER
TYPE
[11]
PULL
UP/DOWN
TYPE
[12]
DSIS
[13]
RX
ACTIVE/
TX
DISABLE
[14]
IO
RET
[15]
AA5
SERDES0_TX2_N
SERDES0_TX2_N
O
0.8 V
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SERDES
SGMII1_TX0_N
O
PCIE1_TX2_N
O
USB0_SSTX1N
O
AA6
SERDES0_TX2_P
SERDES0_TX2_P
O
0.8 V
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SERDES
SGMII1_TX0_P
O
PCIE1_TX2_P
O
USB0_SSTX1P
O
Y4
SERDES0_TX3_N
SERDES0_TX3_N
O
0.8 V
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SERDES
SGMII2_TX0_N
O
PCIE1_TX3_N
O
USB0_SSTX2N
O
Y5
SERDES0_TX3_P
SERDES0_TX3_P
O
0.8 V
VDDA_0P8_SERDES0
,
VDDA_1P8_SERDES0
,
VDDA_0P8_SERDES0
_C
SERDES
SGMII2_TX0_P
O
PCIE1_TX3_P
O
USB0_SSTX2P
O
V2
SOC_SAFETY_ERRORn
SOC_SAFETY_ERRORn
0
IO
OFF
0
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Y1
SPI0_CLK
SPI0_CLK
0
IO
OFF
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
0
UART1_CTSn
1
I
1
I2C2_SCL
2
IOD
IOD
GPIO0_53
7
IO
pad
W3
SPI0_CS0
SPI0_CS0
0
IO
OFF
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
1
UART0_CTSn
2
I
I
GPIO0_51
7
IO
pad
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DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: DRA821U-Q1



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