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DRA821U4...ALM 数据表(PDF) 82 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 82 Page - Texas Instruments |
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82 / 252 page  6.4 Pin Multiplexing Note Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins. Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are associated with peripheral logic functions. Table 6-106, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see Pad Configuration Registers section in Device Configuration chapter in the device TRM. Refer to the respective peripheral chapter in the device TRM for information associated with peripheral signal multiplexing. Note When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided. Note Table 6-106, Pin Multiplexing does not include SerDes signal functions. For more information, refer to the Serializer/Deserializer (SerDes) chapter in the device TRM. Note The PRU contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the PRU chapter in the device TRM. For more information on the I/O cell configurations, see Pad Configuration Registers section in Device Configuration chapter in the device TRM. Table 6-106. Pin Multiplexing ADDR ESS OFFSE T REGISTER NAME BALL NUMB ER MUXMODE[15:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x1C00 0 WKUP_PADCON FIG_0 B6 MCU_OSPI 0_CLK MCU_HYP ERBUS0_ CK WKUP_GP IO0_16 0x1C00 0 PADCONFIG_0 U6 EXTINTn GPIO0_0 0x1C00 4 WKUP_PADCON FIG_1 C8 MCU_OSPI 0_LBCLKO MCU_HYP ERBUS0_ CKn WKUP_GP IO0_17 0x1C00 4 PADCONFIG_1 AA17 RMII1_RX D0 RGMII1_R D0 RMII1_RX D0 MCAN14_T X GPIO0_2 TRC_DATA 9 UART5_TX D MCASP1_ AXR3 GPMC0_A D0 0x1C00 8 PADCONFIG_2 Y15 RMII1_RX D1 RGMII1_R D1 RMII1_RX D1 MCAN14_ RX GPIO0_3 EHRPWM_ TZn_IN2 TRC_DATA 8 UART5_RX D MCASP1_ AXR2 GPMC0_A D1 DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 82 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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