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DRA821U4...ALM 数据表(PDF) 70 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 70 Page - Texas Instruments |
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70 / 252 page  Table 6-83. OSPI0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_OSPI0_RESET_OUT0 OSPI Reset O C6 MCU_OSPI0_RESET_OUT1 OSPI Reset O D5 6.3.18 Hyperbus 6.3.18.1 MCU Domain Table 6-84. HYPERBUS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_HYPERBUS0_CK Hyperbus Differential Clock (positive) O B6 MCU_HYPERBUS0_CKn Hyperbus Differential Clock (negative) O C8 MCU_HYPERBUS0_INTn Hyperbus Interrupt (active low) I D5 MCU_HYPERBUS0_RESETn Hyperbus Reset (active low) Output O D7 MCU_HYPERBUS0_RESETOn Hyperbus Reset Status Indicator (active low) from Hyperbus Memory I C6 MCU_HYPERBUS0_RWDS Hyperbus Read-Write Data Strobe IO B7 MCU_HYPERBUS0_WPn Hyperbus Write Protect (Not in use) O C6, D5 MCU_HYPERBUS0_CSn0 Hyperbus Chip Select 0 O D6 MCU_HYPERBUS0_CSn1 Hyperbus Chip Select 1 O C6 MCU_HYPERBUS0_DQ0 Hyperbus Data 0 IO D8 MCU_HYPERBUS0_DQ1 Hyperbus Data 1 IO C7 MCU_HYPERBUS0_DQ2 Hyperbus Data 2 IO C5 MCU_HYPERBUS0_DQ3 Hyperbus Data 3 IO A5 MCU_HYPERBUS0_DQ4 Hyperbus Data 4 IO A6 MCU_HYPERBUS0_DQ5 Hyperbus Data 5 IO B8 MCU_HYPERBUS0_DQ6 Hyperbus Data 6 IO A8 MCU_HYPERBUS0_DQ7 Hyperbus Data 7 IO A7 6.3.19 GPMC 6.3.19.1 MAIN Domain Table 6-85. GPMC0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPMC0_CLK GPMC clock IO U13 GPMC0_ADVn_ALE GPMC Address Valid (active low) or Address Latch Enable O W20 GPMC0_CLKOUT GPMC clock generated for external synchronization O V14 GPMC0_DIR GPMC Data Bus Signal Direction Control O V21 GPMC0_OEn_REn GPMC Output Enable (active low) or Read Enable (active low) O T18 GPMC0_WEn GPMC Write Enable (active low) O T17 GPMC0_WPn GPMC Flash Write Protect (active low) O AA18 GPMC0_A0 GPMC Address 0 Output. Only used to effectively address 8-bit data non-multiplexed memories OZ W17 GPMC0_A1 GPMC address 1 Output in A/D non-multiplexed mode and Address 17 in A/D multiplexed mode OZ V18 GPMC0_A2 GPMC address 2 Output in A/D non-multiplexed mode and Address 18 in A/D multiplexed mode OZ V20 DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 70 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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